Hot carrier degradation in Triple-RESURF LDMOS with Trenched-Gate

Abstract

This work investigates by TCAD simulation the impact of hot carrier degradation (HCD) in an nLDMOS that uses many topological features. The trenched gate and the triple-RESURF used to optimally reduce the device on-resistance (RON) , triggers DC shifts that easily surpass 10%. We show that using such topologies implicates a narrower safe operating area (SOA)