Testing of the FFT IP core using DE-10 Board for a PMU application

Abstract

Phase measurement is required in electronic applications where a synchronous relationship between the signals needs to be preserved. As the world continues to move towards a Smarter Grid day by day, it has become the necessity to incorporate real-time monitoring of the grid wherein the instantaneous snapshot of the health of the grid can be made available. Traditional electronic systems which are used for time measurement are designed using a classical mixed-signal approach. With the advent of reconfigurable hardware such as field- programmable gate arrays (FPGAs), it is more advantageous for designers to opt for all-digital architecture. This project is about the design and implementation of a part of Phasor Measurement Unit (PMU) Prototype based on FPGA. We focused on the test of the reliability of the 1024- Point altera FFT core to get a spectrum of the input signal and calculate the phasor quantities. A function generator is used for the generation of voltage and current signals which would be passed through the Analog to digital converter and then store the converted data in FIFOs (Sink for input and Source for output) which communicate accordingly with the FFT unit. The system uses the Intel DE10 FPGA board and the Quartus Prime suite to design and implement the system.