Analysis of the gate-to-channel capacitance variation for the tri-gate nanowire junctionless transistors

Abstract

In this paper, the gate-to-channel capacitance variation for the tFlat-band voltageri-gate nanowire junctionless transistor (JLT) has been analyzed. It is based on the 2-D electrostatic numerical simulation realized using Silvaco-TCAD Software. The flat-band voltage and the threshold voltage are extracted trough the plotting of the derivative for the gate-to-channel capacitance versus the gate voltage. This plotting is performed for different values of the channel width and the channel height of the tri-gate JLT. Moreover, the physical effect of the back-gate biasing has been investigated