Kassem, AbdallahWang, J.Khouas, AbdelhakimBoukadoum, Mounir2016-07-032016-07-0320030-7803-7573-4https://dspace.univ-boumerdes.dz/handle/123456789/3036An ultrasound imaging systems require high resolution and real-time processing. The real-time imaging can be achieved using a digital beamforming (DBF) method. One of the main important parts of the DBF is the real-time delay calculation. The design and implementation of a pipelined architecture for the beamforming delay calculation is addressed. The design uses a minimum size look-up memory to store the initial scan information as opposed to previous approaches. The circuit is implemented in CMOS 0.18μm technology and the resulting layout area is 0.5 mm2, while a total power consumption of 20 mWenUltrasoundDigital BeamformingDelay calculationReal-time imagesVariable delay CMOS implementation for ultrasonic beamformingArticle