Kassem, AbdallahWang, J.Khouas, AbdelhakimBoukadoum, Mounir2016-07-032016-07-0320030-7695-1929-6https://dspace.univ-boumerdes.dz/handle/123456789/3037The real-time ultrasonic imaging system can be achieved using a digital beamforming (DBF) method. The critical part of the DBF is the real-time sampled-delay focusing (SDF) which requires a large number of memories (FIFO) to store the scanned information. The sampled-delay focusing technique is used to eliminate the use of the analog delay lines. This paper concerns the design and implementation of a pipelined sampled-delay architecture for ultrasonic digital beamforming. The design uses a minimum size look-up memory to store the initial scan information as opposed to previous approaches. The circuit is implemented in CMOS 0.18􀁐m technology and the resulting active layout area is 0.14 mm2, while its total power consumption is below 40 mWPipelined sampleddelay focusing CMOS implementationultrasonic digital beamformingArticle