Chenouf, AmelDjezzar, BoualemBentarzi, HamidBenabdelmoumene, Abdelmadjid2020-12-222020-12-22202019729283DOI: 10.1049/iet-cds.2019.0307https://ieeexplore.ieee.org/document/9139598https://dspace.univ-boumerdes.dz/handle/123456789/5980This study presents a negative bias temperature instability (NBTI) mitigation design technique for CMOS 6T-static random access memory (6T-SRAM) cells. The proposed approach is based on transistor sizing technique. It consists of sizing the nMOS access transistors of the cell to alleviate NBTI ageing occurring in its pMOS pull-up transistors threatening the cell stability. Once the access transistors are sized for a better hold static noise margin under NBTI, the other transistors of the 6T-SRAM cell could be properly sized for improved read stability and write-abilityenSizingCMOS 6T-SRAM cellNBTI ageing mitigationArticle