HCI degradation of LOCOS-based LDMOS transistor fabricated by 1 μ m CMOS process

Houadef, AliDjezzar, Boualem2022-01-022022-01-022020978-172818292-6https://ieeexplore.ieee.org/document/9249844DOI 10.1109/ICEE49691.2020.9249844https://dspace.univ-boumerdes.dz/handle/123456789/7531Physically based device simulation of hot carrier injection (HCI) degradation is performed. The device under test is a LOCOS (local oxidation of silicon) based, single RESURF (reduced surface field), LDMOS (laterally diffused MOSFET). The transistor is obtained from process simulation, based on 1 μ m CMOS technology available at CDTA. Using the trap degradation model, degradation over time and different biases, the shift of threshold voltage Δ VTH, ON-state resistance (Δ RON, saturation current (Δ IDSat) and device lifetime are extracted. In addition, a quasi-static RF characterization is done for different stress times with a particular focus on flicker noise. The results show that DC parameter shifts are linear but still manageable. However, under RF regimes significant instabilities are encounteredenHot Carrier InjectionLDMOSLOCOSHCI degradation of LOCOS-based LDMOS transistor fabricated by 1 μ m CMOS processOther