Benseddik, Houssem EddineCherki, BrahimHamadouche, M'hamedKhouas, Abdelhakim2021-02-232021-02-23201213058246DOI: 10.1109/ICMCS.2012.6320178https://ieeexplore.ieee.org/document/6320178https://dspace.univ-boumerdes.dz/handle/123456789/6502In this work, we propose real time implementation approaches of distributed Constant False Alarm Rate (CFAR) detection with noncoherent integration. The Cell Averaging (CA-CFAR) and Clutter MAP (CMAP-CFAR) detectors are employed as local detectors. The proposed architecture shows that it can be implemented with the advantages of a parallel structure and allows an important optimization of the required FPGA hardware resources utilization. The structure has been implemented using a Virtex-II XC2V1000-4FG456C FPGA board. The FPGA implementation results are presented and discussedenFPGA-basedMAP-CFARArticle