Amiri, Amir MohammadBoukadoum, MounirKhouas, Abdelhakim2016-06-292016-06-2920061-4244-0417-7https://dspace.univ-boumerdes.dz/handle/123456789/3025This paper presents improvements on a novel FPGAbased multi-hit Time-to-Digital Converter (TDC) to measure time intervals with a resolution of 100ps and a variable dynamic range controlled by a binary coarse counter. We use a matrix topology to provide a two-level resolution, aiming to minimize the overall measurement time. The conventional dead time is eliminated by the continuous detection and processing of data by two delay matrices operating in parallel. A back-resetting scheme eliminates the erroneous multi-detection of an event along matrix tap lines. The circuit was tested on a XILINX SPARTAN-3 FPGA platform.enLow Dead Time,Multi-hit FPGADigital ConverterArticle