Browsing by Author "Lairedj, Abderrezak"

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    Design and implementation of automatic voltage regulator for synchronous generator
    (2021) Saad, Aymane; Lairedj, Abderrezak; Bentarzi, Hamid (Supervisor)
    Automatic Voltage Regulator (AVR) is necessary for all power generation plant producing electricity using synchronous generators (SGs) to ensure constant voltage in the grid connection. This final year project aims to design and implement an AVR using Labview program for the laboratory 1.5kVA salient pole Lab-volt SG. First, an experimental test is carried out using test bench in order to identify the relationship between the terminal voltage of the SG and current injected to the field winding, the second experiment is done to identify the PWM signals needed for different loads connected to the terminal of the generator. Then, AVR model is simulated using Simulink/ Matlab. Finally, a model of the AVR will be constructed and tested under five different loads condition.