Browsing by Author "Saidi, Taki Eddine"

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    Accelerating Stereo Matching on Mutlicore ARM Platform
    (IEEE, 2020) Saidi, Taki Eddine; Khouas, Abdelhakim; Abbes, Amira
    Stereo vision is a well-known technique in computervision used to acquire the 3D depth information of a scenefrom two or more 2D images. One of the main issues with anystereo vision system is how to make a good trade off betweenthe processing speed and the quality of the disparity map. Thisissue can be resolved through the use of dedicated hardwareplatforms, like Field Programmable Gate Arrays and GraphicalProcessing Units, which are considered as expensive solutions.In this work, the challenge of accelerating stereo matching onlow cost multicore platforms is tackled. We present a novelsoftware implementation of a sparse Rank algorithm, that uses amodified Sum of Absolute Differences 1D box filtering algorithmin the correlation stage. Consequently, we reduce the numberof computations and memory space needed for computing thedisparity map. The system is implemented on a multicoreAdvanced Risc Machine platform (ODROID XU4). Experimentalresults show that the system is capable of achieveing a processingspeed of 59 Frames Per Second for images of size320×240pixelswith a disparity range of 20 pixels. Furthermore, the sparse Rankstructure does not affect significantly the overall quality of thedisparity map.
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    Implementation of a real-time stereo vision algorithm on a cost-effective heterogeneous multicore platform
    (WILEY, 2022) Saidi, Taki Eddine; Khouas, Abdelhakim; Amira, Abbes
    Stereo vision is a major computer vision technique commonly used for robotics appli- cations. Existing software implementations of this technique on general-purpose pro- cessors offer low time-to-market compared to other platforms. However, such imple- mentations can hardly achieve real-time and their cost is usually relatively high. These issues can be solved by embedded multicore platforms. In this article, we present a low-cost, improved software implementation of a stereo matching algorithm in the cor- relation stage that combines a sparse rank transform with a combination of sum of absolute differences 1-D and 2-D box filtering algorithms. A circular buffer scheme is used to optimize memory usage during the rank computation stage. The system runs on a heterogeneous multicore platform (ODROID XU4). Through the extensive use of single instruction multiple data Neon intrinsics, the system can process images with a size of 320 × 240 pixels and a disparity range of 20 pixels at a rate of 111 frames per second. The proposed system can be used in mobile robot platforms that require low power consumption while delivering real-time performance.
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    Implementation of real-time stereo vision system
    (Universite M'Hamed Bougara Boumerdès : Institut de Génie Eléctrique et Eléctronique, 2025) Saidi, Taki Eddine; Khouas, Abdelhakim
    Stereo vision is a key computer vision technique widely used in robotics and autonomous driving for reconstructing scene depth from two or more images captured at distinct viewpoints. The core of the stereo vision process is stereo matching, which tries to solve the problem of finding corresponding pixels between stereo images. This stage is computationally intensive, making it challenging to achieve real-time performance on general-purpose processors. Existing implementations in the literature employ specialized hardware platforms to accelerate stereo matching, but this often comes at the expense of flexibility and long development cycles. In this thesis, we propose an efficient Sparse Rank Transform (SRT) algorithm for stereo matching and explore different implementation strategies to balance accuracy, speed, power consumption, and cost. The work includes both software and hardware implementations of the proposed algorithm, as well as a hardware/software co-design system developed for obstacle detection, aiming to combine the benefits of both approaches. The software implementation, running on a heterogeneous multicore platform (ODROID-XU4), introduces a key optimization through the combination of the proposed SRT and a Hybrid-D Box Filtering Algorithm (BFA). The SRT accelerates the rank computation stage, while the Hybrid-D BFA significantly speeds up the sum of absolute differences (SAD) correlation stage by efficiently reusing intermediate computations. Both stages are further optimized using NEON vectorization, which enhances parallelism and boosts overall throughput. This implementation achieves a processing speed of 111 frames per second (fps) for Quarter Video Graphics Array (QVGA) images with a disparity range of 20 pixels, while maintaining good accuracy. The hardware implementation, deployed on a Zynq-7000 System on Chip (SoC) Field Programmable Gate Array (FPGA) (XC7Z020-CLG484), integrates the SRT module within an existing stereo matching architecture and delivers real-time performance that is 21 times faster than the software implementation while consuming significantly less power. To validate the performance of the hardware SRT module in a real-world application, it was integrated into a hardware/software co-design system for obstacle detection. This system combines hardware-based stereo matching with a software detection phase and achieves 128 fps on QVGA images from the Enpeda Image Sequence Analysis Test Site (EISATS) benchmark. The estimated power consumption of 1.9 W demonstrates the energy efficiency of the proposed design, confirming that combining hardware acceleration with software flexibility provides an effective solution for real-time robotics applications such as obstacle avoidance and autonomous navigation