Browsing by Author "Sawan, Mohamad"

Now showing 1 - 4 of 4

Accurate testability analysis based-on multi-frequency test generation and a new testability metric
(IEEE, 2008) Abderrahman, A.; Savaria, Yvon; Khouas, Abdelhakim; Sawan, Mohamad
The effectiveness of testing the analog part of mixed-signal circuits impacts their overall manufacturing cost. Therefore, it is important to have accurate metrics to estimate fault coverage and to precisely measure the test quality. In this paper, we propose an accurate testability analysis based on multi-frequency test pattern generation and a new testability measure called the parameter fault coverage (PFC) that takes into account the continuous characteristic of the parametric faults spectrum and masking effect of process variations. This new analog test metric allows accurately measuring analog test quality and enables taking better decisions regarding the use of design for testability (DFT) techniques. Therefore, poor product test quality and unnecessary design modifications, which may be caused by incorrect fault coverage estimates, can be avoided
Modeling Efficient Inductive Power Transfer Required To Supply Implantable Devices
(2005) Sehil, Mohamed; Sawan, Mohamad; Khouas, Abdelhakim
This paper presents a model for inductively coupled links with an integrated receiver on silicon. To be accurate, this model includes losses related to the integration of the receiver The modelling technique of the receiver coil has been verified using Agilent Momentum Electro-Magnetic simulations. This comprehensive model is employed to obtain maximum power efficiency by performing a discrete optimization of the geometric dimensions of the link coils. The optimized link can deliver 50mW to a visual cortical stimulator and monitoring devices with an efficiency of 21% at a distance of 1cm. The receiver has 4mm of diameter
Multicoils-based inductive links dedicated to power up implantable medical devices: Modeling, design and experimental results
(Springer Science, 2009) Sawan, Mohamad; Hashemi, Saeid; Sehil, Mohamed; Khouas, Abdelhakim
We present in this paper a new topology of inductively-coupled links based on a monolithic multi-coils receiver. A model is built to characterize the proposed structure using Matlab and is verified employing simulation tools under ADS electromagnetic environment. This topology accounts for the losses associated with the receiver micro-coil including substrate and oxide layers. The geometry of micro-coils significantly desensitizes the link to both angular and side misalignments. A custom fabrication process using 1 micron metal thickness is also presented by which two sets of micro-coils varying in the number of coils are realized. The first set possesses one coil 4 mm of diameter and represents a power efficiency close to 4% while the second set possesses multi-coils with an efficiency of 18%. The resulting optimized link can deliver up to 50 mW of power to power up an implantable device either sensor or stimulator. The experimental results for the prototypes are remarkably in agreement with those obtained from simulated models and circuits
New Analog Test Metrics Based on Probabilistic and Deterministic Combination Approaches
(IEEE, 2008) Abderrahman, A.; Sawan, Mohamad; Savaria, Yvon; Khouas, Abdelhakim
The continuous characteristic of the parametric faults spectrum, the process variations and their masking effects are major difficulties limiting the development of efficient test generation for parametric faults. Moreover, there is a need for accurate test metrics to quantify the quality of a test set and to determine whether the testability is adequate. An analog test metric called parameter fault coverage (PFC) was recently introduced by the authors. The PFC metric takes into account the combination of the above major difficulties. In this paper, we consider parametric faults caused by the increased variance in device parameters. We introduce two novel metrics: one is called guaranteed parameter fault coverage (GPFC), which is the guaranteed lower bound of the PFC, and the other one is called partial parameter fault coverage (PPFC), which is the probabilistic component of the PFC. We combine the deterministic metric GPFC and the probabilistic metric PPFC to produce a PFC metric that enables accurately measuring the analog test quality and allows precisely measuring testability, thus avoiding the drawbacks of incorrect decisions regarding the use of design for testability (DFT) techniques. Also, we show that when DFT is used to improve circuit testability, PFC becomes dominated by the deterministic component GPFC, while the probabilistic component PPFC is minimized. This paper demonstrates the effectiveness of our approach on an illustrative example