Browsing by Author "Tahi, Hakim"

Now showing 1 - 10 of 10

An accurate combination of on-the-fly interface trap and threshold voltage methods for NBTI degradation extraction
(Springer, 2014) Tahanout, Cherifa; Tahi, Hakim; Djezzar, Boualem; Benabdelmomene, Abdelmadjid; Goudjil, Mohamed; Nadji, Becharia
Charge Pumping,GeometricComponent and Degradation ParametersExtraction in MOSFETDevices
(IEEE, 2015) Tahi, Hakim; Tahanout, Cherifa; Djezzar, Boualem Djezzar; Boubaaya, Mohamed; Abdelmadjid, Benabdelmoumene; Chenouf, Amel
In this paper, we model the geometric component of charge pumping technique (CP). Base on this proposed model, wehave established ananalyticequation for charge pumping current. This equation seems to be an universal one since it is in agreement with CP experimental data of different technologies devices.Instead the classical considerations regarding a parasitic nature of the geometric component, we have demonstrated, in this work, that it can be used to estimate the negative bias temperature (NBTI)induced mobility degradationusing the charge pumping basedmethods such as on-the-fly interface trap (OTFIT).
Deep Analysis of the Geometric Component in Charge Pumping of Polycrystalline Silicon Thin-Film Transistors
(IEEE, 2015) Tahi, Hakim; Djezzar, Boualem; Tahanout, Cherifa Tahanout; Benmessai, Karim
In this paper, we model the geometric component in a charge pumping (CP) technique of polycrystalline silicon thin-film transistors (poly-Si TFTs). This model is based on both remaining carrier types when the device transits from accumulation to inversion and vice versa. Therefore, it depends on gate length (L) and width (W) as well as on gate signal rise (t f ) and fall time (tf). The proposed model shows good agreement with the experimental data. We have shown that the geometric component due to the remaining carriers, when poly-Si TFT transits from inversion to accumulation, is very small compared with that due to the transition from accumulation to inversion. Consequently, a new analytic CP model, depending on gate width, is developed for n-channel poly-Si TFT.
Etude de la fiabilité des dispositifs MOS soumis à des rayonnements ionisants
(2012) Tahi, Hakim
Les études de la fiabilité et de la qualification des dispositifs MOS, soumis à des irradiations ionisantes, dépendent fortement des techniques et des méthodes utilisées pour l'estimation des pièges induits par irradiation dans ces dispositifs. Jusqu'à aujourd'hui, il n'existe pas de méthodes pour l'estimation distincte des pièges induits par irradiation dans chacune des différentes régions du transistor, notamment la région de l'oxyde du champ (LOCOS : LOCal Oxidation Silicon) et le STI : Shallow Trench Isolation). Cette région est la plus sensible à l'irradiation dans les transistors modernes. En plus, l'estimation des pièges induits par l'irradiation en utilisant les méthodes basées sur le Pompage de Charge (PC) est entachée d'erreurs, dues d'une part, à la contribution des différentes régions du canal au courant maximal du PC utilisé pour cette estimation, et d'autre part, au courant géométrique qui augmente avec l'irradiation. Ces problèmes sont traités et résolus dans ce travail. Dans la première partie de ce travail, nous avons validé expérimentalement la méthode OTCP (Oxide Trap based on Charge Pumping) qui a été développée dans notre laboratoire. Nous avons montré que cette méthode est plus adaptée à l'estimation des pièges induits par l'irradiation dans les transistors à canal long par rapport aux méthodes classiques, telles que : C(VG), STS, MG, DTCP et DTBT. Par la suite, nous avons développé une méthodologie pour adapter la méthode OTCP à l'extraction des pièges induits par irradiation dans les transistors à canal court. Dans la deuxième partie, nous avons montré que le courant maximal du PC dans les transistors est la contribution des courants pompés dans les régions constituant le canal et le courant géométrique. Enfin, nous avons développé une nouvelle méthode pour éliminer la composante géométrique dans les mesures du PC des transistors vierges et irradiés et une autre méthode pour l'estimation des pièges induits par l'irradiation dans les différentes régions constituant le canal du transistor
Experimental investigation of NBTI degradation in power VDMOS transistors under low magnetic field
(IEEE, 2017) Tahi, Hakim; Tahanout, Cherifa; Boubaaya, Mohamed; Djezzar, Boualem; Merah, Sidi Mohammed; Nadji, Bacharia; Saoula, Nadia
Investigation of NBTI degradation on power VDMOS transistors under magnetic field
(IEEE, 2014) Tahi, Hakim; Benmessai, Karim; Le Floch, Jean Michel; Boubaaya, Mohamed; Tahanout, Cherifa; Djezzar, Boualem; BENABDELMOMENE, Abdelmadjid; Goudjil, Mohamed; Chenouf, Amel
In this paper, we report an experimental evidence of the impact of applied a low magnetic field (B<;100 Gauss) during negative bias temperature instability (NBTI) stress and recovery, on commercial power double diffused MOS transistor (VDMOS). We show that both interface (ΔN it ) and oxide trap (ΔN ot ) induced by NBTI stress decrease by applied magnetic field. This decrease is more pronounced as the magnetic field is high. In addition, the recovery of NBTI induced threshold voltage shift (ΔV th ) is relatively important with applied magnetic field.
Measurement of Square Resistance In Situ of SnO2: F Thin Film With Annealing at High Temperature Under Air
(ICTP, 2008) Tahi, Hakim; Boumaour, Messaoud; Tala-Ighil, Razika; Belkaid, M. S.
Thin films of fluorine doped tin oxide (SnO2: F), deposited by spray pyrolysis on silicon substrate, were characterized by the method of four points probe in situ during annealing at high temperature under air. The evolution of square resistance (in situ) with the annealing temperature was interpreted in terms of competition between electronic conduction and ionic conduction. A square resistance of 136�/□ is measured before annealing and after annealing at 900°C, the square resistance increases appreciably to reach 40k�/□. This increase is explained by the absorption of oxygen at the films surface and an increase in SiO2 thickness at interface SnO2/Si
On the Circuit-Level Reliability Degradation Due to AC NBTI Stress
(IEEE Transactions on Device and Materials Reliability, 2016) Chenouf, Amel; Djezzar, Boualem; Benabdelmoumene, Abdelmadjid; Tahi, Hakim
In this paper, an experimental analysis of the impactof dynamic negative bias temperature instability (NBTI) stresson the CMOS inverter dc response and temporal performanceis presented. We analyzed the circuit behavior subjected to acNBTI in the prospect to correlate the induced degradation withthat seen at PMOS device level. The results revealed that, whileac NBTI-induced shift of the inverter features shows both voltageand temperature dependence, it does not always exhibit stresstime dependence. Indeed, the time exponentnis found to dependon both voltage and temperature. The analysis of such behaviorwhen correlated with the PMOS threshold shift points towardthe coexistence of more than one physical mechanism behindthe degradation, where one mechanism could dominate the otherunder certain stress conditions. Depending on these conditions,circuit lifetime could be more or less affected
Oxide trap annealing by H2 cracking at e'center under NBTI stress
(IEEE, 2012) Tahanout, Cherifa; Nadji, Becharia; Tahi, Hakim; Djezzar, Boualem; Benabdelmoumene, Abdelmadjid; Chenouf, Amel
Simple and fast simulation approach to investigate the NBTI effect on suspended gate MOS devices
(2019) Tahanout, Cherifa; Tahi, Hakim; Bouchera, Nadji; Hocini, Lotfi
In this paper, we investigate the negative bias temperature instability(NBTI) on conventional P-type metal-oxide-semiconductorfield effecttransistors (PMOSFET) using on-fly bulk trap technique (OTFBT). Theextracted NBTI induced interface (ΔNit)andoxidetraps(ΔNot), usingOTFBT, are modelled and used to simulate the NBTI effect on N-typesuspended gate metal-oxide-semiconductor devices (N-type SG-MOS),which could be manufactured by thesamefabricationprocessasconventional PMOSFET. The used approach to simulate the NBTI effectis performed by combining, in the same simulation program, theN-type SG-MOS devices model with the NBTI inducedΔNitandΔNotmodels. This approach allowed us to simulate and predict rapidly thelifetime of the N-type SG-MOS devices subjected to the NBTI degrada-tion. The simulation shows that the degradation of N-type SG-MOSdevices due to the NBTI is the same as that of conventional PMOSFET.However, the extracted lifetime of N-type SG-MOS devices (stiction ofthe suspended gate) is longer than that of conventional PMOSFET.