Publications Scientifiques

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Author: search.filters.author.Khouas, AbdelhakimEnd date: 2009

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    Speed-up of high accuracy analog test stimulus optimization
    (1999) Khouas, Abdelhakim; Derieux, Anne
    Analog integrated circuit testing and diagnosis is a very challenging problem. The inaccuracy of measurements, the infinite domain of possible values and the parameter deviations are among the major difficulties. During the process of optimizing production tests, Monte Carlo simulation is often needed due to parameter variations, but because of its...
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    Methodology for Fast and Accurate Analog Production Test
    (1999) Khouas, Abdelhakim; Derieux, Anne
    This paper describes a new technique to reduce the number of simulations required during analog fault simulation. The method takes into account process parameter variations and aims to reduce the number of the computational expensive Monte Carlo simulations often required during analog fault simulation. In section I a review of the state of the art.
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    Speed-up of High Accurate Analog Test Stimulus
    (1999) Khouas, Abdelhakim; Derieux, Anne
    Analog integrated circuit testing and diagnosis is a very challenging problem. The inaccuracy of measurements, the innite domain of possible values and the parameter deviations are among the major diOEculties. During the process of optimizing production tests, Monte Carlo simulation is often needed due to parameter variations, but because of its expensive computational cost, it becomes the bottleneck of such a process. This paper describes a new technique to reduce the number of simulations required during analog fault simulation. This leads to the optimization of production tests subjected to parameter variations. In section I a review of the state of the art is presented, section II introduces the algorithm and describes the methodology of our approach. The results on CMOS 2-stage opamp and conclusions are given in sections III and IV
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    Analog Fault Detection based on Statistical Analysis
    (Hal, 2000) Khouas, Abdelhakim; Derieux, Anne
    In analog circuits, process variations result in physical parameter variations. Simulated values must then be considered with there tolerance intervals. Consequently, contrarily to digital circuits where the outputs are either '0' or '1' such that we can decide without ambiguity whether a fault is detectable or not, for analog circuits the fault detectability is a vague problem as the fault can either be completely detectable, partially detectable or completely undetectable which makes it very diOEcult to take a decision. In order to solve this decision problem, we have introduced the probability to detect fault (PDF) function which allows to formalize the problem of analog fault detection under parameter variations
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    Optimized Statistical Analog Fault Simulation
    (2001) Khouas, Abdelhakim; Dessouky, Mohamed; Derieux, Anne
    A new statistical method for analog fault simulation is presented. The method takes into account process parameter variations and aims to reduce the number of the computational expensive Monte Carlo simulations often required during analog fault simulation. The technique is illustrated by means of a fifth-order low-pass switched-capacitor filter
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    Investigation of single cell delay and delay mismatch in ring oscillator based test structure
    (2006) Zhou, Bo; Amiri, Amir Mohammad; Khouas, Abdelhakim
    In previous work, we presented a test structure based on ring oscillator (RO) to measure single cell delay and delay mismatch, which can provide reliable information on intra-die and inter-die parameter variations. A delay cell of the configurable RO in the test structure considered for the computation technique consists of an inverter and a conducting transmission gate between adjacent cells. This paper will analyze the effects on delay cells of the transmission gates connecting to the output of inverters included in the active RO and investigate in depth delay mismatch in this RO based test structure. Monte Carlo simulation results reveal that the computation technique is applicable to derive delay mismatch between delay cells. A large number of post-layout simulations for different layout structures with different number of cells and different transistor sizes have been performed to analyze delay mismatch related to interconnect and device parameter variations
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    Fault Simulation for Analog Circuits Under Parameter Variations
    (2000) Khouas, Abdelhakim; Derieux, Anne
    Analog integrated circuit testing and diagnosis is a very challenging problem. The inaccuracy of measurements, the infinite domain of possible values and the parameter deviations are among the major difficulties. During the process of optimizing production tests, Monte Carlo simulation is often needed due to parameter variations, but because of its expensive computational cost, it becomes the bottleneck of such a process. This paper describes a new technique to reduce the number of simulations required during analog fault simulation. This leads to the optimization of production tests subjected to parameter variations. In Section 1 a review of the state of the art is presented, Section 2 introduces the algorithm and describes the methodology of our approach. The results on CMOS 2-stage opamp and Fifth-order Low-pass switched-capacitor Filter are given in Sections 3 and conclusions in Section 4
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    FDP: fault detection probability function for analog circuits
    (IEEE, 2001) Khouas, Abdelhakim; Derieux, A.
    In analog integrated circuits, process variations result in physical parameter variations. Simulated performance values must then be considered with their tolerance intervals. Consequently, contrarily to digital circuits where the outputs are either '0 or ' 1' such that we can decide without ambiguity whether a fault is detectable or not, for analog circuits fault detectability is still a vague problem since the fault can either be completely detectable, partially detectable or completely undetectable which makes it very difficult to take a decision. In order to solve this decision problem, we have introduced the fault detection probability (FDP) function which allows to formalize the problem of analog fault detection subjected to parameter variations
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    Pipelined sampled-delay focusing CMOS implementation for ultrasonic digital beamforming
    (IEEE, 2003) Kassem, Abdallah; Wang, J.; Khouas, Abdelhakim; Boukadoum, Mounir
    The real-time ultrasonic imaging system can be achieved using a digital beamforming (DBF) method. The critical part of the DBF is the real-time sampled-delay focusing (SDF) which requires a large number of memories (FIFO) to store the scanned information. The sampled-delay focusing technique is used to eliminate the use of the analog delay lines. This paper concerns the design and implementation of a pipelined sampled-delay architecture for ultrasonic digital beamforming. The design uses a minimum size look-up memory to store the initial scan information as opposed to previous approaches. The circuit is implemented in CMOS 0.18􀁐m technology and the resulting active layout area is 0.14 mm2, while its total power consumption is below 40 mW