Publications Scientifiques
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Item Implementation of a real-time stereo vision algorithm on a cost-effective heterogeneous multicore platform(WILEY, 2022) Saidi, Taki Eddine; Khouas, Abdelhakim; Amira, AbbesStereo vision is a major computer vision technique commonly used for robotics appli- cations. Existing software implementations of this technique on general-purpose pro- cessors offer low time-to-market compared to other platforms. However, such imple- mentations can hardly achieve real-time and their cost is usually relatively high. These issues can be solved by embedded multicore platforms. In this article, we present a low-cost, improved software implementation of a stereo matching algorithm in the cor- relation stage that combines a sparse rank transform with a combination of sum of absolute differences 1-D and 2-D box filtering algorithms. A circular buffer scheme is used to optimize memory usage during the rank computation stage. The system runs on a heterogeneous multicore platform (ODROID XU4). Through the extensive use of single instruction multiple data Neon intrinsics, the system can process images with a size of 320 × 240 pixels and a disparity range of 20 pixels at a rate of 111 frames per second. The proposed system can be used in mobile robot platforms that require low power consumption while delivering real-time performance.Item Speed-up of high accuracy analog test stimulus optimization(1999) Khouas, Abdelhakim; Derieux, AnneAnalog integrated circuit testing and diagnosis is a very challenging problem. The inaccuracy of measurements, the infinite domain of possible values and the parameter deviations are among the major difficulties. During the process of optimizing production tests, Monte Carlo simulation is often needed due to parameter variations, but because of its...Item Methodology for Fast and Accurate Analog Production Test(1999) Khouas, Abdelhakim; Derieux, AnneThis paper describes a new technique to reduce the number of simulations required during analog fault simulation. The method takes into account process parameter variations and aims to reduce the number of the computational expensive Monte Carlo simulations often required during analog fault simulation. In section I a review of the state of the art.Item Speed-up of High Accurate Analog Test Stimulus(1999) Khouas, Abdelhakim; Derieux, AnneAnalog integrated circuit testing and diagnosis is a very challenging problem. The inaccuracy of measurements, the innite domain of possible values and the parameter deviations are among the major diOEculties. During the process of optimizing production tests, Monte Carlo simulation is often needed due to parameter variations, but because of its expensive computational cost, it becomes the bottleneck of such a process. This paper describes a new technique to reduce the number of simulations required during analog fault simulation. This leads to the optimization of production tests subjected to parameter variations. In section I a review of the state of the art is presented, section II introduces the algorithm and describes the methodology of our approach. The results on CMOS 2-stage opamp and conclusions are given in sections III and IVItem Analog Fault Detection based on Statistical Analysis(Hal, 2000) Khouas, Abdelhakim; Derieux, AnneIn analog circuits, process variations result in physical parameter variations. Simulated values must then be considered with there tolerance intervals. Consequently, contrarily to digital circuits where the outputs are either '0' or '1' such that we can decide without ambiguity whether a fault is detectable or not, for analog circuits the fault detectability is a vague problem as the fault can either be completely detectable, partially detectable or completely undetectable which makes it very diOEcult to take a decision. In order to solve this decision problem, we have introduced the probability to detect fault (PDF) function which allows to formalize the problem of analog fault detection under parameter variationsItem Optimized Statistical Analog Fault Simulation(2001) Khouas, Abdelhakim; Dessouky, Mohamed; Derieux, AnneA new statistical method for analog fault simulation is presented. The method takes into account process parameter variations and aims to reduce the number of the computational expensive Monte Carlo simulations often required during analog fault simulation. The technique is illustrated by means of a fifth-order low-pass switched-capacitor filterItem FPGA-based real-time implementation of distributed system CA-CFAR and Clutter MAP-CFAR with noncoherent integration for radar detection(IEEE, 2012) Benseddik, Houssem Eddine; Cherki, Brahim; Hamadouche, M'hamed; Khouas, AbdelhakimIn this work, we propose real time implementation approaches of distributed Constant False Alarm Rate (CFAR) detection with noncoherent integration. The Cell Averaging (CA-CFAR) and Clutter MAP (CMAP-CFAR) detectors are employed as local detectors. The proposed architecture shows that it can be implemented with the advantages of a parallel structure and allows an important optimization of the required FPGA hardware resources utilization. The structure has been implemented using a Virtex-II XC2V1000-4FG456C FPGA board. The FPGA implementation results are presented and discussedItem Hardware Design and FPGA Implementation for Road Plane Extraction Based on V-disparity Approach(2015) Benacer, Imad; Hamissi, Aicha; Khouas, AbdelhakimAccurate and real-time free space and obstacles detection is a task of great interest to the navigation of mobile robots, and the integration to existing vehicle's safety systems. This paper presents a novel approach for road plane extraction, free space and obstacles discrimination using stereovision. The estimated road profile from V-disparity images allows robust extraction of the road features from pixels classification of the disparity map. The proposed hardware architecture combines parallel processing with dedicated and optimized modules to reduce logic resource utilization, and accelerate processing time. This architecture is implemented on Cyclone IV E FPGA based prototyping board, and tested using real stereoscopic images of different environments. Experimental results demonstrate the efficiency and accuracy of the proposed method. The implemented system can treat up to 490 and 122 frames/s for stereoscopic images of 320×240 and 640×480 pixels respectivelyItem Blind source separation based phase estimator for carrier synchronization of high-order QAM signals(IEEE, 2015) Chouiha, Mustapha; Khouas, Abdelhakim; Belouchrani, Adel; Baudoin, GenevièveIn this paper, a new carrier synchronization loop for high-order QAM signals has been proposed in which a blind source separation algorithm for carrier phase tracking is used as phase estimator in feed-back configuration. When used for large constellation schemes, simulations show that the proposed solution achieves better phase tracking and improves performance of the carrier phase tracking loop in terms of bit error rate versus energy per bit to noise ratio (BER vs Eb/N0) comparing to the descent algorithm and to Decision Directed synchronizerItem An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware(IEEE, 2019) Guettatfi, Zakarya; Platzner, Marco; Kermia, Omar; Khouas, AbdelhakimExecuting real-time tasks on FPGAs involves interdependent placement and scheduling problems. Most presented approaches model tasks as rectangles and allow for placing tasks anywhere on the FPGA. Such models are, however, not supported by commercial technology and tool flows. We present a new approach for mapping periodic real-time tasks to FPGAs based on micro slots, which are aggregated to reconfigurable slots that can accommodate a task at a time. This model enables us to leverage existing real-time scheduling results, but also poses new problems of reconfigurable slot creation and layout generation and, most importantly, lends itself to a practical realization. We discuss our overall approach, detail heuristics for reconfigurable slot creation and layout generation, and present simulation experiments