Browsing by Author "Boubaaya, Mohamed"

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Charge Pumping,GeometricComponent and Degradation ParametersExtraction in MOSFETDevices
(IEEE, 2015) Tahi, Hakim; Tahanout, Cherifa; Djezzar, Boualem Djezzar; Boubaaya, Mohamed; Abdelmadjid, Benabdelmoumene; Chenouf, Amel
In this paper, we model the geometric component of charge pumping technique (CP). Base on this proposed model, wehave established ananalyticequation for charge pumping current. This equation seems to be an universal one since it is in agreement with CP experimental data of different technologies devices.Instead the classical considerations regarding a parasitic nature of the geometric component, we have demonstrated, in this work, that it can be used to estimate the negative bias temperature (NBTI)induced mobility degradationusing the charge pumping basedmethods such as on-the-fly interface trap (OTFIT).
Experimental investigation of NBTI degradation in power VDMOS transistors under low magnetic field
(IEEE, 2017) Tahi, Hakim; Tahanout, Cherifa; Boubaaya, Mohamed; Djezzar, Boualem; Merah, Sidi Mohammed; Nadji, Bacharia; Saoula, Nadia
Fast methods for studying the effect of electrical stress on SiO2 dielectrics in Metal-Oxide-Semiconductor Field-Effect transistors
(Pleiades Publishing, 2023) Messaoud, Dhia Elhak; Djezzar, Boualem; Boubaaya, Mohamed; Chenouf, Amel; Benabdelmoumene, Abdelmadjid; Zatout, Boumediene; Zitouni, Abdelkader
This work implements three fast measurement techniques based on the measure–stress–measure (MSM) method. These techniques, namely, measuring–around–, one–point on–the–fly (OTF), and pulsed current-voltage (PIV), were used to characterize three different technologies of metal–oxide–semiconductor field-effect transistors (MOSFETs) with same gate dielectric silicon–dioxide (SiO2) and various thicknesses = 20 nm, 4 nm, 2.3 nm. Moreover, well–configured electrical stress biasing has been performed to discuss the dielectric degradation of these devices using those characterization techniques. The pros and cons of the used techniques are well discussed based on our results. Furthermore, experimental results showed that threshold voltage shift () follows a power law time dependence with time exponent (n) being 0.16 for molecular hydrogen (H2) diffusing species and 0.25 for hydrogen atoms (H) diffusing species. We have found that the thicker the SiO2 dielectric the more the oxide traps () contribute to the resulting degradation. However, the dependency between SiO2 dielectric thickness and oxide traps could not be necessarily linear.
Investigation of NBTI degradation on power VDMOS transistors under magnetic field
(IEEE, 2014) Tahi, Hakim; Benmessai, Karim; Le Floch, Jean Michel; Boubaaya, Mohamed; Tahanout, Cherifa; Djezzar, Boualem; BENABDELMOMENE, Abdelmadjid; Goudjil, Mohamed; Chenouf, Amel
In this paper, we report an experimental evidence of the impact of applied a low magnetic field (B<;100 Gauss) during negative bias temperature instability (NBTI) stress and recovery, on commercial power double diffused MOS transistor (VDMOS). We show that both interface (ΔN it ) and oxide trap (ΔN ot ) induced by NBTI stress decrease by applied magnetic field. This decrease is more pronounced as the magnetic field is high. In addition, the recovery of NBTI induced threshold voltage shift (ΔV th ) is relatively important with applied magnetic field.
Metal-oxide-semiconductor field-effect transistor (MOSFET) pulsed current-voltage characterization technique: design and discussion
(Pleiades Publishing, 2023) Messaoud, Dhia Elhak; Djezzar, Boualem; Boubaaya, Mohamed; Benabdelmoumene, Abdelmadjid; Zatout, Boumediene; Chenouf, Amel; Zitouni, Abdelkader
In this paper, we implement the pulsed current–voltage (PIV) technique for the metal-oxide-semiconductor field-effect transistor (MOSFET) device’s ultrafast characterization based on the OpAmp amplifier OPA818. The latter dropped down the measurement time for a whole MOSFET characteristic to = 50 ns as an enhancement. Furthermore, a study concerning the technique’s dependency on measurement time (), channel length (), and channel width () is accomplished. It is found that the distortion in the technique’s results, labeled as hysteresis, is inversely proportional to measurement time and it increases dramatically with very low values of . Also, the results show that PIV could have a somehow direct proportionality to channel length, and it is justified by the gate/drain capacitance () effect. On the other hand, the technique shows no dependency on channel width at all. Moreover, as measurements limitations, the results couldn’t record drain currents less than ≈ 10–7 A, this makes PIV limited to the study of threshold voltage degradation () only. However, this issue is well discussed and solutions have been proposed.
NBTI Fast Electrical Characterization in pMOSFET Devices
(Université M'hamed Bougara de Boumerdès : Laboratory of Signals and Systems, 2021) Dhia Elhak, Messaoud; Djezzar, Boualem; Benabdelmoumene, Abdelmadjid; Boubaaya, Mohamed; Zatout, Boumediene; Zitouni, Abdelkader
To measure the entire characteristic of p-MOSFET, we have implemented the fast Ids-Vgs technique. The latter is used to study NBTI phenomenon with measure-stress-measure method, for electric field 5MV/cm < Eox < 7.5MV/cm, and temperatures 27°C < Ts < 120°C. Measurement time has reached 10 us, and a stress-measure delay (switching time) of about a hundred of milliseconds was obtained. However, strengths and weaknesses of the implemented technique have been discussed. Furthermore, the extraction methods: transconductance (Gm), subthreshold slope (SS), and mid-gap (MG), have been implemented and discussed as well. NBTI parameter i.e. Delta Vth, n, gamma and Ea were extracted and compared to other results. A time exponent n of 0.149 has been touched. Activation energy Ea = 0.039 eV and a field factor gamma = 0.41 MV/cm for a stress time ts < 10 s have been obtained.
Single pulse charge pumping technique improvement for interface-states profiling in the channel of MOSFET devices
(IEEE Transactions on Electron Devices, 2023) Messaoud, DhiaElhak; Djezzar, Boualem; Boubaaya, Mohamed; Benabdelmoumene, Abdelmadjid; Zatout, Boumediene; Chenouf, Amel; Zitouni, Abdelkader
This paper presents the separated single pulse charge pumping (SSPCP) technique, an improvement over conventional single pulse charge pumping (CSPCP) for analyzing metal oxide semiconductor field-effect transistor (MOSFET) degradation. SSPCP separates the measurement of source and drain currents (Is and Id ), enabling the localization of interface traps (Nit) near these regions. Experimental validation shows that SSPCP achieves comparable results to CSPCP with a maximum measurement error of 5%. The technique is particularly useful for studying stress-induced localized degradation profiling, allowing for the exploration of non-uniform stress (e.g., hot-carrier injection) and uniform stress (e.g., negative bias temperature instability) in transistors with short channels. SSPCP effectively analyzes localized degradation and identifies differences in stress-induced degradation between the source and drain regions, making it a valuable tool in semiconductor device characterization.
Single Pulse Charge Pumping Technique Improvement for Interface-States Profiling in the Channel of MOSFET Devices
(2023) Messaoud, Dhia Elhak; Djezzar, Boualem; Boubaaya, Mohamed; Benabdelmoumene, Abdelmadjid; Zatout, Boumediene; Chenouf, Amel; Zitouni, Abdelkader
This paper presents the separated single pulse charge pumping (SSPCP) technique, an improvement over conventional single pulse charge pumping (CSPCP) for analyzing metal oxide semiconductor field-effect transistor (MOSFET) degradation. SSPCP separates the measurement of source and drain currents $({I}_{ {s}}$ and ${I}_{ {d}}$ ), enabling the localization of interface traps $({N}_{ {it}})$ near these regions. Experimental validation shows that SSPCP achieves comparable results to CSPCP with a maximum measurement error of 5%. The technique is particularly useful for studying stress-induced localized degradation profiling, allowing for the exploration of non-uniform stress (e.g., hot-carrier injection) and uniform stress (e.g., negative bias temperature instability) in transistors with short channels. SSPCP effectively analyzes localized degradation and identifies differences in stress-induced degradation between the source and drain regions, making it a valuable tool in semiconductor device characterization.