Computer
Permanent URI for this collectionhttps://dspace.univ-boumerdes.dz/handle/123456789/3082
Browse
14 results
Search Results
Item Emulating multi-node embedded systems using Renode(Université M’hamed Bougara de Boumerdes : Institut de Genie Electrique et Electronique, 2024) Hachemane, Abderrahmane; Khouas, Aness Mohamed; Maache, Ahmed (Supervisor)Emulation is crucial prior to high-scale, complicated embedded systems, particularly for pedagogical and prototype utilization. The emulation process offers an ideal and cost-effective approach, where we can be in a position to analyze and evaluate system designs with the as-sumptions and some flaws that can be worked out befor eimplementing the minthe actual sys-tem. This practice helps greatly in teaching since students can train on such concepts without the necessity of having costly hardware. This project introduces Renode, which is an effective emulation tool, to emulate an entire. embedded system including interconnected-node systems. Fast prototyping and the emulation of various hardware elements, including their functionality, flexibility, an dinteractive communications, make Renode a versatile platform for development. Our work starts with implementing a single-node embedded system using ZedBoard and Free RTOS, demonstrating the basic setup and functionality. We then expanded this implementation to accurately emulate a multi-node system, highlighting Renode’s ability to handle complex, interconnected environments. In fact, as our finding sindicate, Renode is avaluable an defficient tool for modeling embedded systems and Iot networks. The emulations were effective and the approach proved to be sound in practice despite several difficulties that were metal on the way.Item Deep neural network acceleration using Intel NIOS-II custom instructions.(Université M’hamed Bougara de Boumerdes : Institut de Genie Electrique et Electronique, 2024) Boudraa, Nadjib; Mihoubi, ,Djenet Yasmine; Maache, Ahmed (Supervisor)The rapid advancement of Artificia lIntelligence (AI ) hasled to its integration into various fields, including embedded systems, which present unique challenges due to constraint sin storage, power consumption, and the need for realtime execution. To optimize AI performance in these environments, we propose a hardware acceleration system. This system incorporates a floating point unit and lookup tables for Sigmoid and Leaky-ReLU activation functions, both designed using HDL and implemented on a Field Programmable Gate Array (FPGA) with the Nios II soft processor and its custom instructions. We tested this system on a Deep Neural Network (DNN) written in C and trained it multiple times with varying numbers of layers. The results were remarkable, with some networks experiencing performance improvements of over 60%. However, as the model’s complexity increased with additional layers, the acceleration benefi tdecreased, dropping to around 10% in the most complex scenarios. Despite this reduction in acceleration for highly complex models, our system remains reliable and efficient, demonstrating its potential for critic alreal-time embedded AIapplications.Item Hardware/Software co-design framework for distributed computing with FPGA-based computing nodes(Université M’hamed Bougara de Boumerdes : Institut de Genie Electrique et Electronique, 2023) Lehamel, Lotfi; Kharoubi, Abdennour; Maache, Ahmed (Supervisor)In the distributed computing field ,FPG Aintegratio nca noff ersignific antspeedups and power efficien cy inma nyapplication s.T hecomplexi ty ofcooperati nghardware and software into a single system remains a limiting factor in clustering FPGAs in a distributed computing environment. In this work, a distributed system that offer susers a framework to configur ean dinterfac ewit hmultipl eFPG Aboard swa sdesigne dand implemented. The system consists of a server connected to several Terasic DE10 FPGA boards on a local network, while a custom messaging protocol built on top of TCP/IP is used for communication. The system was built with two factors in mind: flexibility ,a sin its ability to adapt to various application requirements; and scalability, in which it can support multiple users and multiple computing nodes. In terms of testing, a load-free performance benchmark was conducted on each component of the system separately to observe the system overhead on the user application. Using a matrix multiplier test-case application, the system was tested on localhost to avoid networking hardware limitation. As a result, the system showed a low overhead on the user application while its behavior followed a logical pattern. Incorporating more computing hardware led to an increase in the total throughput reaching up to 8.6 Gbps and a decrease in the latency overhead. To evaluate the achieved results on the test-case application using the system, a comparison with a software implementation of the same application was conducted. The test-case application on the system performed up to 1.3, 5.5, and 11.5 times faster using 4, 16, and 36 nodes, respectively, compared to the software-based implementation.Item Design and Evaluation of AES based Video Encryption/Decryption using FPGA-HPS(2021) Touati, Anouar; Ouali, Ayoub; Maache, Ahmed (Supervisor)The internet is an open and public system where information is send and received over shared wires and connections. Though we still exchange a lot of private data, things like credit card numbers, bank information, passwords, and emails. Especially during this pandemic, data exchange increased drastically due to the radical shift in the ways people communicate and engage with one another. Schools adopted online education, whereas employees are working from home. Virtual classrooms, webinars, and online meetings on video chat applications like zoom, google, and facebook have become the new normal of today’s world. Protecting and securing this tremendous amount of data in transit requires strong cryptographic algorithms. One of the most popular and widely used data protection schemes nowadays across the globe is The Advanced Encryption Algorithm (AES). However, security alone does not fulfil the requirements of modern systems, where speed is considered being an integral part of every design. The aim of our project is not to implement the AES-128 algorithm but to maximize its performance while using it in a video recording encryption/decryption application within the constrained embedded hardware of the Terasic DE10 Standard FPGA Board. Therefore, we have started our experiment by a pure software implementation of the AES-128 in C language, and then we created multiple design versions of the hybrid system that make use of the SoC HPS and FPGA. Finally, we implemented the fastest designs in a video encryption/decryption application. The results showed that the hybrid system has the advantage of faster execution by a factor of over 4 times when compared to the pure C implementation, which makes it a favorable choice in this type of applications on this platform.Item Implementation of a ROS based hand gesture controlled robot control(2021) Kehoul, Mohamed Islem; Rahmouni, Takieddine; Maache, Ahmed (Supervisor)This project consists of designing and building a hand gesture-controlled robot arm platform. The appropriate hardware equipment suitable for the desired tasks and for the robot arm movement are selected. Moreover, the robot arm architecture is designed. Then, the Robot Operating System (ROS) is used for the software implementation, synchronization and communication of the system. The first ROS node which recognize the hand gestures is coded on the laptop whereas the second node which controls the servos of the robot is build on the raspberry pi. The data is sent to second node in real time to generate appropriate control signals for the robot servos. The robot arm is 3DItem Ceramic tiles classification using OpenCV under Embedded Linux(2021) Bouakaz, Djihad Nacereddine; Maache, Ahmed (Supervisor)The proposed project consists in developing a real-time system for automatic inspection of moving ceramic tiles and detection and identification of their surface defects at high-speed using OpenCV and FPGA HPS. Based on vision techniques, the system will consist of a lighting device (LEDs) and a LDR to provide the suitable lighting environment, camera, and embedded Linux running on FPGA DE10 board to create an image processing hardware and software environment. It will allow the visualization of the surface and by means of a data base, it will detect and proceed to the identification of the defects of surface during the production cycle. This process classifies ceramic tiles automatically and allows for making the necessary corrections in due time.Item FPGA-Based phasor measurement unit prototype(2020) Hamrit, Yazid Taha; Maache, Ahmed (Supervisor)This report describes the design and implementation of an SoPC-based Pha-sor Measurement unit which is required in electronic applications where a syn-chronous relationship between the signals needs to be preserved, using the Field Programmable Gate Array (FPGA). However, due to the constraints imposed by the covid19 health crisis, the project only covered the evaluation usage of the FFT core using an analogue input from a potentiometer. This signal is sampled using the Analog to Digital Converters(ADC) on the FPGA board. The design then stores digital data into a local FIFO, which is passed to a 1024-Point FFT hardware core to get the spectrum of the signal and hence calculate the main frequency. The sys-tem uses the Intel DE10 FPGA board (donated by the Intel University Program) and the Quartus Prime suite to design and implement the system and the model was synthesized using Quartus II and targeted at Cyclone-V FPGA. The design was successfully implemented.Item Design and implementation of IOT system based LoRa(2020) Djadir, Mohamed. I. M.; Maache, Ahmed (Supervisor)The internet of things (IOT) is one of the most growing technologies in the last few years. However, this technology increases the demand for connected devices. Various standards are currently contending to gain an edge over the competition and provide the massive connectivity that will be required by a world in which everyday objects are expected to communicate with each other. Among these standards, Low-Power Wide Area Networks (LPWANs) are continuously gaining momentum, mainly thanks to their ability to provide long-range coverage to devices,exploiting license-free frequency bands. LoRa is emerging as one of the most promising LPWAN, since it enables the energy-constraint devices distributed over wide areas to establish affordable connectivity. However, how to implement a cost-effective and flexible LoRa network is still an open challenge. This project aims to design and implement a prototype for a low cost LoRa network for IOT application. The network prototype will be designed based on the five-layer conventional IOT architecture. Our design will include hardware and software implementation of a LoRa end node, single-channel LoRa gateway and a network server. Furthermore, we implement a new transmission protocol between the end node and the gateway based on the variation of the LoRa module parameter. In addition, our implementation also includes a data handling system that collects the data from the network server and save it to the cloud.Item Fire suppression system based on MATLAB video processing and FPGA(2016) Messi, Salaheddine; Bourouis, Bilal; Maache, Ahmed (Supervisor)Class A fires (fires out of wood, paper, cloth…etc) are the most common firebreaks in confined space, such as houses, desks, schools…etc. In this project a quick and reliable automatic fire suppression system is designed and implemented. It uses a camera to monitor the confined space at all times. Image processing techniques are used to treat the video stream and starts an alarm whenever a fire is detected. The system uses RGB components to detect the RGB characteristics of fire, and uses luminance and color information stored in YCbCr components to confirm the rules of detection. The system can locate the fire with high precision based on the geographic location of camera and location of fire pixels in the image. After locating the fire an FPGA board is instructed to point a water cannon towards the fire source. But first Confirms the fire using a flame sensor, then an alarm is started and water is ejected from the cannon. The whole process takes matter of some seconds before action is taken. The system has proved itself to be very accurate in small monitored spaces as traced in the objectives. Further improvement have to be made before it can be installed in almost any institution where class A fires can be a risk.Item FPGA-Based real-time video processing framework(2016) Bekka, Larbi; Tayeb Cherif, Nassim; Maache, Ahmed (Supervisor)FPGAs are widely used in academic and corporate research, they are more than a good fit when it comes to real-time embedded image/video processing due to their flexibility and the parallelism they offer which is one of the needed features in image processing algo-rithms. The aim of this project is to build a framework for real-time embedded image/video pro-cessing on FPGAs for academic research in our institute. This report presents a background in image processing and the hardware platform used and discusses the parts of the accomplished work. In this part of the project, we designed and implemented hardware modules in Verilog HDL that perform low level image processing operations and image data acquisition. These mod-ules are an intensity calculator, a Sobel filter, a Laplacian filter, a gradient calculator, a mean filter, and a scalable 3-line buffer. An SRAM frame buffer was also designed and implemented where a single frame is saved for later retrieval. These modules were implemented and tested on an Altera DE2 board. The images were captured by a Sony DSC-W120 digital camera (an off-the-shelf camera) and streamed to the board in NTSC video format.