Computer

Permanent URI for this collectionhttps://dspace.univ-boumerdes.dz/handle/123456789/3082

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    Big data compression
    (2022) Boulkhiout, Mouaad; Hafri, Adel; Sadouki, Leila (Supervisor)
    In order to make data storage more effective and to use up less storage space, data can be compressed. Additionally, data compression helps speed up the transmission of data exchange. Currently, a variety of techniques can be employed to data compression Moreover, the outcomes and approaches of each treatment vary. The comparison of data compression will be covered in this essay. We present a detailed analysis of Five separate algorithms, Shannon-Fano, Run-Length Encoding, the Huffman Algorithm, the LZW Algorithm, and the DELTA Algorithm. To address these issues, there is a growing need for greater data compression and communication theory research. Such study addresses the needs of fast data transfer through networks. This study focuses on deep learning analysis of the most widely used picture compression methods.
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    FPGA assisted 3D iso-surface extraction
    (2016) Koussa, Amira; Kanoune, Amel; Namane, Rachid (superviseur)
    Extracting Iso-surfaces from large 3D medical images is a very time consuming task. In this work we investigate if this process can be accelerated using a field programmable gate array (FPGA). A CPU-based isosurface extractor system has been implemented in several works using different approaches. One of the techniques by which we are interested is a modified Dividing Cubes algorithm based on an incremental search strategy for generating all points of the desired iso surface. This method involves a lot of iterative arithmetic calculations. We aim to use the FPGA to offload expensive, re-occurring calculations from the CPU by performing them on the FPGA and then transferring back the results to the computer before visualizing the generated 3D surface.
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    FPGA based VGA controller and arcade games
    (2016) Lakhdari, Zineb; Elkhabazi, Hayet; Benzekri, A. (Supervisor)
    This report describes the design and implementation of an FPGA-based VGA controller and arcade games. The hardware modules are developed in the Very High Speed Hardware Description Language (VHDL) and implemented onto the FPGA of the low-cost DE2 board. As a standard interface, Video Graphic Array VGA has been widely used. The system displays on the VGA monitor a menu which consists of two games (pong & breakout games), where the user is able to choose any one of them. The first game is a two player game, they are controlling paddles to punch a moving ball to the opponent's side. Whereas the second game is a one player game, in which he controls a moving paddle to bounce the ball trying to destroy all the bricks that are situated on the top of screen. During the course of this project we added some modifications such as the adjustment of the paddles and ball’s speed, yet the text generation like the score of players, the menu selection. The results show that the proposed algorithms give good performance with short processing time, low resource utilization, small power consumption and memory usage. Because the data can be sent directly to monitors, the design improve system reliability in real time and save hardware resource.
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    FPGA-Based real-time video processing framework
    (2016) Bekka, Larbi; Tayeb Cherif, Nassim; Maache, Ahmed (Supervisor)
    FPGAs are widely used in academic and corporate research, they are more than a good fit when it comes to real-time embedded image/video processing due to their flexibility and the parallelism they offer which is one of the needed features in image processing algo-rithms. The aim of this project is to build a framework for real-time embedded image/video pro-cessing on FPGAs for academic research in our institute. This report presents a background in image processing and the hardware platform used and discusses the parts of the accomplished work. In this part of the project, we designed and implemented hardware modules in Verilog HDL that perform low level image processing operations and image data acquisition. These mod-ules are an intensity calculator, a Sobel filter, a Laplacian filter, a gradient calculator, a mean filter, and a scalable 3-line buffer. An SRAM frame buffer was also designed and implemented where a single frame is saved for later retrieval. These modules were implemented and tested on an Altera DE2 board. The images were captured by a Sony DSC-W120 digital camera (an off-the-shelf camera) and streamed to the board in NTSC video format.
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    Remote control of an SoPC-Based self-parking car
    (2016) Abdi, Yasmine; Ounnoughi, Amira; Benzekri, K. (supervisor)
    This report describes the design process of a remote control SoPC-based self-parking car. The remote control operations are done using an Android application running on a Smartphone and communicating with the digital controller via Bluetooth wireless technology. Distance measurements are obtained from Infrared sensors disposed on the car. The car performs three parking modes namely: parallel, perpendicular and reverse parking. The approach used to design the digital controller is the system-on-programmable-chip (SoPC) technique. This latter integrates a Nios II soft core processor, intellectual property (IP) cores and custom logic components designed in VHDL, all in the same chip. In addition to remotely controlling the system, the Android application serves as a graphical user interface (GUI), allowing the user to follow the operations of the ongoing parking mode performed by the car. The digital controller developed with Altera Quartus II 9.1 sp2 Web Edition software development suite tools is realized on a Cyclone-II EP2C35F672C6 FPGA platform to verify its feasibility and functionality. Additional hardware circuitry of the system is implemented on a Protoboard.
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    Fiche _Like Mobile Robot implementation
    (2018) Groune, Meriem; Sedoud, Amrou; Belaidi
    Due to the increasing demand for environmental sustainability, significant attention has been paid to aquatic environmental monitoring using autonomous underwater robot. This project aims at constructing a biologically inspired fish- like robot. The robot is designed to be capable of propelling itself through oscillations of a flexible caudal fin, like a real underwater fish. The actuation system and the sensing system are introduced, studied then designed. The robot has three actuation systems for locomotion, including the buoyancy system used to pump water in and out of the robot’s body to change the net buoyancy (we used a ventilator operating by DC motor in this project), and the actively-controlled tail fin system used to control the turning motion and heading orientation, a servomotor is used for this objective in this project.
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    Face recognition using convolutional neural networks
    (Université M’Hamed BOUGARA de Boumerdes : Institut de génie electrique et electronique (IGEE), 2017) Azizi, Narimene; Benselim, Mohammed Amine
    Face Recognition is a currently developing technology with multiple real-life applications. Deep learning, in particular Convolutional Neural Networks, has achieved promising results in Face Recognition recently. The goal of this project is to implement a complete Face Recognition system based on state-of-the art Convolutional Neural Networks, and to test it on effected images in unconstrained environments. Relevant facial features are extracted and used to determine if pairs of face images belong to the same individual or not. These features allow to compare faces between them in an efficient way. The system is trained using two different datasets, Faces94 and FaceScrub, resulting in two models. The "Labeled Faces in the Wild" benchmark is used for testing and evaluating the performance of the two models. A comparison with classical methods is also done.