Institut de Génie Electrique et d'Electronique

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    FPGA based VGA controller and arcade games
    (2016) Lakhdari, Zineb; Elkhabazi, Hayet; Benzekri, A. (Supervisor)
    This report describes the design and implementation of an FPGA-based VGA controller and arcade games. The hardware modules are developed in the Very High Speed Hardware Description Language (VHDL) and implemented onto the FPGA of the low-cost DE2 board. As a standard interface, Video Graphic Array VGA has been widely used. The system displays on the VGA monitor a menu which consists of two games (pong & breakout games), where the user is able to choose any one of them. The first game is a two player game, they are controlling paddles to punch a moving ball to the opponent's side. Whereas the second game is a one player game, in which he controls a moving paddle to bounce the ball trying to destroy all the bricks that are situated on the top of screen. During the course of this project we added some modifications such as the adjustment of the paddles and ball’s speed, yet the text generation like the score of players, the menu selection. The results show that the proposed algorithms give good performance with short processing time, low resource utilization, small power consumption and memory usage. Because the data can be sent directly to monitors, the design improve system reliability in real time and save hardware resource.
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    FPGA-Based real-time video processing framework
    (2016) Bekka, Larbi; Tayeb Cherif, Nassim; Maache, Ahmed (Supervisor)
    FPGAs are widely used in academic and corporate research, they are more than a good fit when it comes to real-time embedded image/video processing due to their flexibility and the parallelism they offer which is one of the needed features in image processing algo-rithms. The aim of this project is to build a framework for real-time embedded image/video pro-cessing on FPGAs for academic research in our institute. This report presents a background in image processing and the hardware platform used and discusses the parts of the accomplished work. In this part of the project, we designed and implemented hardware modules in Verilog HDL that perform low level image processing operations and image data acquisition. These mod-ules are an intensity calculator, a Sobel filter, a Laplacian filter, a gradient calculator, a mean filter, and a scalable 3-line buffer. An SRAM frame buffer was also designed and implemented where a single frame is saved for later retrieval. These modules were implemented and tested on an Altera DE2 board. The images were captured by a Sony DSC-W120 digital camera (an off-the-shelf camera) and streamed to the board in NTSC video format.