Institut de Génie Electrique et d'Electronique
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Item FPGA based microstepping controller.(Université M’hamed Bougara de Boumerdes : Institut de Genie Electrique et Electronique, 2023) Rahal, Chahira; Benzekri, A. (Supervisor)This project describes the design, simulation and implementation of an FPGA-based microstepping driver to control a dual H-Bridge to properly commutate a bipolar perma- nent magnet stepper motor for precise-position tracking applications. The kernel of the driver is a microstepping mode algorithm implemented in two ROMs as look-up tables.This engine is used to generate the appropriate pulse width modulation (PWM) signals to control the current levels in the motor’s windings. Because the current patterns in the win- dings closely resemble sine waves with 90° phase shift, we used a sinusoidal (sine/cosine) approximations function to build the look-up table to drive the motor’s windings. The digital driver is developed with the Very high speed integrated circuit Hardware Descrip- tion Language (VHDL). The driver is synthesized using Quartus® II, the Intel®- FPGA software development suite tools, and targeted at an FPGA of the Cyclone-II family. Computer simulations are carried on Quartus II simulator. The results show the effec- tiveness and merit of this design process by testing several fractions of a full step (1/2,1/4 and 1/8). In addition, the real-time applicability of this driver is exemplifie do na permanent magnet bipolar stepper motor.Item FPGA Based Control of Three Level NPC Inverter(Université M’Hamed BOUGARA de Boumerdes : Institut de génie electrique et electronique (IGEE), 2016) Khenfer, Zoubir; METIDJI, B. (supervisor)Power electronics is the technology associated with efficient conversion, control and conditioning of electric power from its available input in to the desired electrical output form. The actual work falls into this scope presenting an FPGA based control and implementation of three levels voltage NPC inverter. The Multi-Carrier Sinusoidal Pulse Width Modulation (MC-SPWM) is the control method adopted in order to digitize power so that a sequence of voltage pulses can be generated by the on and off of the power switches. writing a VHDL code of the adopted modulation technique ,checking the code on MODELSIM software then loading the code to the FPGA kit through QUARTUS environment are the carried steps in order to end up with the right switching signals. The design and implementation of the appropriate gate drive circuitry is a the next step in order to assure a suitable driving circuit that is required to supply the necessary charge to the power valves gates . Using this control method and the gate driving circuitry along with the specified topology of the three levels NPC inverter leads to the desired results of this works. Results that are presented and discussed.Item FPGA-based arabic LCD display controller IP design(2016) Rahil, Lillia; Aggoune, Khedidja; Khouas, A. (Supervisor)A 2x16 character Liquid Cristal Display (LCD) is one of the most common Input/Output (I/O) devices. It allows designers to communicate with the outside world. Alphanumeric LCD can display English and some other special characters. However, Arabic characters cannot be displayed since the Arabic fonts are not embedded in the LCD controller, thus there are no corresponding American Standard Code for Information Interchange (ASCII) codes for it. To allow Arabic display on an LCD module and reduce designs’ time, we suggest to create an Intellectual Property (IP) core for Arabic character LCD display controller. The design was done by creating a block diagram of the LCD controller and interface it to a clock divider module and an IP core memory namely a Block Random Access Memory (BRAM). The whole design was initialized and tested using VHDL codes. The LCD initialization is done using some specific commands. These commands allow Arabic characters to be generated and read from the Character Generator RAM (CG RAM) which is one of the controller’s memory regions. The complete LCD module was described and synthesized using Xilinx Integrated Synthesis Environment (ISE) design suite tools, and implemented and tested using Xilinx Virtex 5 Field Programmable Gate Array (FPGA) and Digilent Genesys board. After creating the needed design, a simulation of each component has been made using a test bench VHDL code. However, Displaying Arabic characters using FPGA couldn’t be achieved due to lack of time and some problems, mainly changing the FPGA board, wasting time in working on some other Xilinx tools and lack of the needed documentations. Moreover, once we implemented the design LCD displayed just a cursor blinking to show clearly that the generated character couldn’t be displayed .It has not been well introduced in the CGRAM of the controller. What we suggest is to try to reuse those commands and test it once again since the same method works once we tested it on a microcontroller.Item FPGA-Based car-like robot path follower with obstacle avoidance(2016) Moulay, Aicha; Laoufi, Fatima; Benzekri, A.(Supervisor)This project is about the design and implementation of an SOPC based automated path following with obstacle avoidance using infrared sensors and ultrasonic sensor. The Line follower robot is a mobile machine that can detect and follow the line drawn on the floor. The path is predefined as a black line on a white surface with a high contrasted color. This kind of robot should sense the path using infrared sensors which installed under the robot. After that the data is transmitted to the controller to be processed by specific transition buses. The processor is going to send proper commands to the driver unit circuit and thus the path will be followed by the line follower robot. This system is provided with obstacle avoidance mechanism using ultrasonic sensor. After avoiding the obstacle either from the right side or the left side the car then has to find its path again to reach its destination with the continuity of following and scanning the path. The car will stop if an obstacle is detected on the path and on both sides of it or if the path is ended. The digital controller is designed and implemented using both off-the-shelf integrated circuits and the FPGA. The FPGA subsystem is developed using Altera Quartus II development suite tools and the Altera monitor program software. It is realized on a CycloneII EP2C35F672C6 low-cost FPGA platform and tested on a physical structure constructed in the laboratory for its feasibility and functionality.