Publications Scientifiques

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    Single pulse charge pumping technique improvement for interface-states profiling in the channel of MOSFET devices
    (IEEE Transactions on Electron Devices, 2023) Messaoud, DhiaElhak; Djezzar, Boualem; Boubaaya, Mohamed; Benabdelmoumene, Abdelmadjid; Zatout, Boumediene; Chenouf, Amel; Zitouni, Abdelkader
    This paper presents the separated single pulse charge pumping (SSPCP) technique, an improvement over conventional single pulse charge pumping (CSPCP) for analyzing metal oxide semiconductor field-effect transistor (MOSFET) degradation. SSPCP separates the measurement of source and drain currents (Is and Id ), enabling the localization of interface traps (Nit) near these regions. Experimental validation shows that SSPCP achieves comparable results to CSPCP with a maximum measurement error of 5%. The technique is particularly useful for studying stress-induced localized degradation profiling, allowing for the exploration of non-uniform stress (e.g., hot-carrier injection) and uniform stress (e.g., negative bias temperature instability) in transistors with short channels. SSPCP effectively analyzes localized degradation and identifies differences in stress-induced degradation between the source and drain regions, making it a valuable tool in semiconductor device characterization.
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    Single Pulse Charge Pumping Technique Improvement for Interface-States Profiling in the Channel of MOSFET Devices
    (2023) Messaoud, Dhia Elhak; Djezzar, Boualem; Boubaaya, Mohamed; Benabdelmoumene, Abdelmadjid; Zatout, Boumediene; Chenouf, Amel; Zitouni, Abdelkader
    This paper presents the separated single pulse charge pumping (SSPCP) technique, an improvement over conventional single pulse charge pumping (CSPCP) for analyzing metal oxide semiconductor field-effect transistor (MOSFET) degradation. SSPCP separates the measurement of source and drain currents $({I}_{ {s}}$ and ${I}_{ {d}}$ ), enabling the localization of interface traps $({N}_{ {it}})$ near these regions. Experimental validation shows that SSPCP achieves comparable results to CSPCP with a maximum measurement error of 5%. The technique is particularly useful for studying stress-induced localized degradation profiling, allowing for the exploration of non-uniform stress (e.g., hot-carrier injection) and uniform stress (e.g., negative bias temperature instability) in transistors with short channels. SSPCP effectively analyzes localized degradation and identifies differences in stress-induced degradation between the source and drain regions, making it a valuable tool in semiconductor device characterization.
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    Process and performance optimization of Triple-RESURF LDMOS with Trenched-Gate
    (Wiley, 2021) Houadef, Ali; Djezzar, Boualem
    In this article, we investigate by TCAD simulation, the combination triple reduced surface field (triple-RESURF) and trenched-gate to design an n-type laterally diffused metal-oxide-semiconductor (LDMOS) transistor with high performance. While similar structures reported in the literature, on the one hand, use either the triple-RESURF or trenched-gate at once, on the other hand, those features require at least one additional mask each. We have been able to achieve both features in one transistor with only eight masks at the front-end of line (FEOL), and one less annealing. Therefore, our proposition will be cheaper and provide better performance. The structure is obtained by re-organizing the process steps, re-using other existing masks, and exploiting positive and negative photoresist photolithography. The resulting specific on-state resistance (RON,SP) is 94 mΩmm2, and the breakdown voltage (BV) is 71 V. But, most importantly a high transconductance (gm) at high gate voltages, with acceptable off-state leakage current (Ioff), which translates into better RF performance overall than what is reported in the literature. The maximum oscillation frequency (fMAX) and cut-off frequency (fT) could reach up to 76 and 43 GHz, respectively. Our device targets fully integrated IoT ASICs that require power amplifiers
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    Oxide trap annealing by H2 cracking at e'center under NBTI stress
    (IEEE, 2012) Tahanout, Cherifa; Nadji, Becharia; Tahi, Hakim; Djezzar, Boualem; Benabdelmoumene, Abdelmadjid; Chenouf, Amel