Publications Scientifiques

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    Accelerating Stereo Matching on Mutlicore ARM Platform
    (IEEE, 2020) Saidi, Taki Eddine; Khouas, Abdelhakim; Abbes, Amira
    Stereo vision is a well-known technique in computervision used to acquire the 3D depth information of a scenefrom two or more 2D images. One of the main issues with anystereo vision system is how to make a good trade off betweenthe processing speed and the quality of the disparity map. Thisissue can be resolved through the use of dedicated hardwareplatforms, like Field Programmable Gate Arrays and GraphicalProcessing Units, which are considered as expensive solutions.In this work, the challenge of accelerating stereo matching onlow cost multicore platforms is tackled. We present a novelsoftware implementation of a sparse Rank algorithm, that uses amodified Sum of Absolute Differences 1D box filtering algorithmin the correlation stage. Consequently, we reduce the numberof computations and memory space needed for computing thedisparity map. The system is implemented on a multicoreAdvanced Risc Machine platform (ODROID XU4). Experimentalresults show that the system is capable of achieveing a processingspeed of 59 Frames Per Second for images of size320×240pixelswith a disparity range of 20 pixels. Furthermore, the sparse Rankstructure does not affect significantly the overall quality of thedisparity map.
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    Investigation of single cell delay and delay mismatch in ring oscillator based test structure
    (2006) Zhou, Bo; Amiri, Amir Mohammad; Khouas, Abdelhakim
    In previous work, we presented a test structure based on ring oscillator (RO) to measure single cell delay and delay mismatch, which can provide reliable information on intra-die and inter-die parameter variations. A delay cell of the configurable RO in the test structure considered for the computation technique consists of an inverter and a conducting transmission gate between adjacent cells. This paper will analyze the effects on delay cells of the transmission gates connecting to the output of inverters included in the active RO and investigate in depth delay mismatch in this RO based test structure. Monte Carlo simulation results reveal that the computation technique is applicable to derive delay mismatch between delay cells. A large number of post-layout simulations for different layout structures with different number of cells and different transistor sizes have been performed to analyze delay mismatch related to interconnect and device parameter variations
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    Over effective hard real-time hardware tasks scheduling and allocation
    (IEEE, 2015) Guettatfi, Zakarya; Kermia, Omar; Khouas, Abdelhakim
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    Fault Simulation for Analog Circuits Under Parameter Variations
    (2000) Khouas, Abdelhakim; Derieux, Anne
    Analog integrated circuit testing and diagnosis is a very challenging problem. The inaccuracy of measurements, the infinite domain of possible values and the parameter deviations are among the major difficulties. During the process of optimizing production tests, Monte Carlo simulation is often needed due to parameter variations, but because of its expensive computational cost, it becomes the bottleneck of such a process. This paper describes a new technique to reduce the number of simulations required during analog fault simulation. This leads to the optimization of production tests subjected to parameter variations. In Section 1 a review of the state of the art is presented, Section 2 introduces the algorithm and describes the methodology of our approach. The results on CMOS 2-stage opamp and Fifth-order Low-pass switched-capacitor Filter are given in Sections 3 and conclusions in Section 4
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    FDP: fault detection probability function for analog circuits
    (IEEE, 2001) Khouas, Abdelhakim; Derieux, A.
    In analog integrated circuits, process variations result in physical parameter variations. Simulated performance values must then be considered with their tolerance intervals. Consequently, contrarily to digital circuits where the outputs are either '0 or ' 1' such that we can decide without ambiguity whether a fault is detectable or not, for analog circuits fault detectability is still a vague problem since the fault can either be completely detectable, partially detectable or completely undetectable which makes it very difficult to take a decision. In order to solve this decision problem, we have introduced the fault detection probability (FDP) function which allows to formalize the problem of analog fault detection subjected to parameter variations
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    Pipelined sampled-delay focusing CMOS implementation for ultrasonic digital beamforming
    (IEEE, 2003) Kassem, Abdallah; Wang, J.; Khouas, Abdelhakim; Boukadoum, Mounir
    The real-time ultrasonic imaging system can be achieved using a digital beamforming (DBF) method. The critical part of the DBF is the real-time sampled-delay focusing (SDF) which requires a large number of memories (FIFO) to store the scanned information. The sampled-delay focusing technique is used to eliminate the use of the analog delay lines. This paper concerns the design and implementation of a pipelined sampled-delay architecture for ultrasonic digital beamforming. The design uses a minimum size look-up memory to store the initial scan information as opposed to previous approaches. The circuit is implemented in CMOS 0.18􀁐m technology and the resulting active layout area is 0.14 mm2, while its total power consumption is below 40 mW
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    Variable delay CMOS implementation for ultrasonic beamforming
    (IEEE, 2003) Kassem, Abdallah; Wang, J.; Khouas, Abdelhakim; Boukadoum, Mounir
    An ultrasound imaging systems require high resolution and real-time processing. The real-time imaging can be achieved using a digital beamforming (DBF) method. One of the main important parts of the DBF is the real-time delay calculation. The design and implementation of a pipelined architecture for the beamforming delay calculation is addressed. The design uses a minimum size look-up memory to store the initial scan information as opposed to previous approaches. The circuit is implemented in CMOS 0.18μm technology and the resulting layout area is 0.5 mm2, while a total power consumption of 20 mW
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    Spurs modeling in direct digital period synthesizers related to phase accumulator truncation
    (IEEE, 2005) Izouggaghen, Badre; Khouas, Abdelhakim; Savaria, Yvon
    This paper presents an analytic model of the spurious noise frequencies in Direct Digital Period Synthesizer (DDPS) due to phase accumulator truncation. DDPS is a new technique for frequency synthesis that takes advantage of the speed and low jitter of a delay-lockedloop- based frequency multipliers and the ability to digitally control the frequency from the direct digital synthesis technique DDS [1-2]. The most important source of spurious noise frequencies in a DDPS circuit is the truncation of the output of its phase accumulator. Computing spectral analysis of DDPS circuit is a CPU time consuming task. Based on series of analytic calculations, a general and simple mathematical formula of the location of spurious frequencies and their magnitudes is predicted. This formula will help designers analyze and develop new DDPS circuits faster
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    A complete spurs distribution model for direct digital period synthesizers
    (IEEE, 2005) Salomon, Max-Elie; Khouas, Abdelhakim; Savaria, Yvon
    This paper presents a new, fully automated algorithm modeling the spurious frequencies in direct digital period synthesizers (DDPS). DDPS is a frequency synthesis technique that combines the speed and low jitter of a delay-locked-loop-based frequency multiplier, with the ability to digitally control the frequency. The algorithm is based on an analysis of the periodicity of the output signal produced by a DDPS circuit on which a time-domain Fourier analysis is performed. The resulting spectrum reflects two major known sources of spurious frequencies in DDPS: accumulator output truncation and delay line cell mismatch. Comparisons with results obtained from time-consuming simulations performed with SIMULINK and processed by FFT were performed to validate the model. An efficient implementation of the proposed algorithm allows comparing many different operating conditions that could not be analyzed with the SIMULINK model due to excessive processing time