Publications Scientifiques
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Item Single pulse charge pumping technique improvement for interface-states profiling in the channel of MOSFET devices(IEEE Transactions on Electron Devices, 2023) Messaoud, DhiaElhak; Djezzar, Boualem; Boubaaya, Mohamed; Benabdelmoumene, Abdelmadjid; Zatout, Boumediene; Chenouf, Amel; Zitouni, AbdelkaderThis paper presents the separated single pulse charge pumping (SSPCP) technique, an improvement over conventional single pulse charge pumping (CSPCP) for analyzing metal oxide semiconductor field-effect transistor (MOSFET) degradation. SSPCP separates the measurement of source and drain currents (Is and Id ), enabling the localization of interface traps (Nit) near these regions. Experimental validation shows that SSPCP achieves comparable results to CSPCP with a maximum measurement error of 5%. The technique is particularly useful for studying stress-induced localized degradation profiling, allowing for the exploration of non-uniform stress (e.g., hot-carrier injection) and uniform stress (e.g., negative bias temperature instability) in transistors with short channels. SSPCP effectively analyzes localized degradation and identifies differences in stress-induced degradation between the source and drain regions, making it a valuable tool in semiconductor device characterization.Item An Analytical Approach for Evaluating Turn-On Switching Losses in SiC MOSFET With Kelvin Pin: Concept and Implementation(Institute of Electrical and Electronics Engineers Inc, 2024) Mohammed Cherif, okba; Nadji, Bouchra; Tadjer, Sid Ahmed; Bencherif, HichemWith the progressive adoption of silicon carbide (SiC) power devices in modern power converters, exploiting their superior efficiency, faster switching speed, and higher power density, an understanding of the factors influencing these properties becomes vital. One such critical factor is switching losses, which can drastically affect overall system performance. This study develops and presents a new analytical model for predicting the turn-on switching losses in SiC MOSFETs with Kelvin pin. The proposed model, derived from a carefully constructed set of nonlinear differential equations, accounts for the nonlinearity of the transconductance by incorporating a novel transfer characteristic model. The model also incorporates the nonlinear junction capacitances effects. The developed analytical model allows for the prediction and optimization of turn-on switching losses in SiC MOSFETs, thus enabling improved energy efficiency and reliability. The accuracy of the proposed model is verified through comparison with experimental results obtained using the double pulse test board that was designed and constructed, demonstrating its applicability for the investigation of SiC MOSFET power lossesItem An Analytical Approach for Evaluating Turn-On Switching Losses in SiC MOSFET With Kelvin Pin: Concept and Implementation(IEEE, 2024) Okba, Mohammed Cherif; bouchra, Nadji; Tadjar, S A; Bencherif, HichemWith the progressive adoption of silicon carbide (SiC) power devices in modern power converters, exploiting their superior efficiency, faster switching speed, and higher power density, an understanding of the factors influencing these properties becomes vital. One such critical factor is switching losses, which can drastically affect overall system performance. This study develops and presents a new analytical model for predicting the turn-on switching losses in SiC MOSFETs with Kelvin pin. The proposed model, derived from a carefully constructed set of nonlinear differential equations, accounts for the nonlinearity of the transconductance by incorporating a novel transfer characteristic model. The model also incorporates the nonlinear junction capacitances effects. The developed analytical model allows for the prediction and optimization of turn-on switching losses in SiC MOSFETs, thus enabling improved energy efficiency and reliability. The accuracy of the proposed model is verified through comparison with experimental results obtained using the double pulse test board that was designed and constructed, demonstrating its applicability for the investigation of SiC MOSFET power losses.Item Single Pulse Charge Pumping Technique Improvement for Interface-States Profiling in the Channel of MOSFET Devices(2023) Messaoud, Dhia Elhak; Djezzar, Boualem; Boubaaya, Mohamed; Benabdelmoumene, Abdelmadjid; Zatout, Boumediene; Chenouf, Amel; Zitouni, AbdelkaderThis paper presents the separated single pulse charge pumping (SSPCP) technique, an improvement over conventional single pulse charge pumping (CSPCP) for analyzing metal oxide semiconductor field-effect transistor (MOSFET) degradation. SSPCP separates the measurement of source and drain currents $({I}_{ {s}}$ and ${I}_{ {d}}$ ), enabling the localization of interface traps $({N}_{ {it}})$ near these regions. Experimental validation shows that SSPCP achieves comparable results to CSPCP with a maximum measurement error of 5%. The technique is particularly useful for studying stress-induced localized degradation profiling, allowing for the exploration of non-uniform stress (e.g., hot-carrier injection) and uniform stress (e.g., negative bias temperature instability) in transistors with short channels. SSPCP effectively analyzes localized degradation and identifies differences in stress-induced degradation between the source and drain regions, making it a valuable tool in semiconductor device characterization.Item Process and performance optimization of Triple-RESURF LDMOS with Trenched-Gate(Wiley, 2021) Houadef, Ali; Djezzar, BoualemIn this article, we investigate by TCAD simulation, the combination triple reduced surface field (triple-RESURF) and trenched-gate to design an n-type laterally diffused metal-oxide-semiconductor (LDMOS) transistor with high performance. While similar structures reported in the literature, on the one hand, use either the triple-RESURF or trenched-gate at once, on the other hand, those features require at least one additional mask each. We have been able to achieve both features in one transistor with only eight masks at the front-end of line (FEOL), and one less annealing. Therefore, our proposition will be cheaper and provide better performance. The structure is obtained by re-organizing the process steps, re-using other existing masks, and exploiting positive and negative photoresist photolithography. The resulting specific on-state resistance (RON,SP) is 94 mΩmm2, and the breakdown voltage (BV) is 71 V. But, most importantly a high transconductance (gm) at high gate voltages, with acceptable off-state leakage current (Ioff), which translates into better RF performance overall than what is reported in the literature. The maximum oscillation frequency (fMAX) and cut-off frequency (fT) could reach up to 76 and 43 GHz, respectively. Our device targets fully integrated IoT ASICs that require power amplifiersItem Oxide trap annealing by H2 cracking at e'center under NBTI stress(IEEE, 2012) Tahanout, Cherifa; Nadji, Becharia; Tahi, Hakim; Djezzar, Boualem; Benabdelmoumene, Abdelmadjid; Chenouf, AmelItem Why is oxide-trap charge-pumping method appropriate for radiation-induced trap depiction in MOSFET?(2009) Djezzar, B.; Tahi, H.; Mokrani, A.Radiation-induced traps, which are generally identified using specific extraction methods, play an important role in the reliability of MOS devices. In this paper, the oxide-trap-based-on-charge-pumping (OTCP) method is used to estimate radiation-induced oxide, interface, and border traps in complementary N- and P-MOS transistors. We emphasize on the critical comparison between the OTCP and classical methods like subthreshold slope (STS), midgap (MG), capacitance-voltage (CV), dual-transistor CP (DTCP), and DT border trap (DTBT), giving a clear insight on the benefits and limitations of OTCP. According to experimental data, the OTCP method is often more accurate than the classical methods. On one side, OTCP offers more accurate densities of radiation-induced interface traps (DeltaN it) and border traps (DeltaN bt), while STS and MG overestimate DeltaN it because both interface and border traps are sensed like interface traps. On the other side, OTCP estimates DeltaN it, DeltaN bt, and oxide trap (DeltaN ot) for N- and P-MOSFETs separately, while DTCP and DTBT give average densities for whole N- and P-MOS devices. Finally, DeltaN ot obtained by OTCP is in excellent agreement with that given by CV. However, they show a slight discrepancy in the DeltaN it extraction