Thèses de Doctorat et Mémoires de Magister
Permanent URI for this communityhttps://dspace.univ-boumerdes.dz/handle/123456789/17
Browse
2 results
Search Results
Item Automatic voltage regulator performance enhancement in power generation(Université M'Hamed Bougara : Institut de génie électrique et électronique, 2023) Ahcene, Fazia; Bentarzi, Hamid(Directeur de thèse)The generation of electrical energy in power systems and islanded networks is generally ensured by the synchronous machine, and hence the enhancement of its dynamic performance during disturbances is increasingly required. The main objective of this research work is to enhance the dynamic performance by maintaining its terminal voltage constant during any instability. This voltage regulation can be ensured via a well-known controller named automatic voltage regulator (AVR) that is generally based on proportional integral (PI) controller. In the first proposed approach, an optimization method such as the particle swarm optimization algorithm (PSO) has been applied to determine the regulator parameters. However, in the second developed method, the AVR is based on Active Disturbance Rejection Control (ADRC) that allows controlling uncertain systems, where the dynamic is not well known such as in this application. Both approaches are tested using different generators with two different ratings under different operating conditions. The first designed AVR is implemented; simulation and test have been carried out under three different operating load conditions using micro-generators such as a 1.5 kVA and 175 W synchronous laboratory power machine with salient pole. This AVR is based on PI controller tuned by PSO algorithm; the obtained simulation and experimental results validate the use of the designed AVR. Then, the second designed AVR test of a second generator of 187 k VA with different exciting system is investigated. However, the designed AVR of the second machine is tested using both techniques PSO base PI and ADRC, the obtained simulation results encourage to use the ADRC control in such applicationItem Reliability aware design of integrated circuits(Université M'Hamed Bougara : Institut de génie électrique et électronique, 2021) Chenouf, Amel; Bentarzi, Hamid(Directeur de thèse)The striking advances in both computer-aided integrated circuit design and manufacturing technologies have paved the way for designing and manufacturing highly complex, high-performance chips integrating more than 100 million transistors into a few square millimeters of silicon. However, this high density has brought with it more challenges for IC designers in terms of their circuits reliability sign-off. In fact, due to the aggressive scaling, and to wear out effects, the electrical parameters of semiconductor devices are shifting over time, causing for ICs the failure to meet the specifications for which they were designed. However, a technology-based solution is not always feasible, mainly because semiconductor engineers usually focus on developing smaller, faster, and less energy-intensive transistors. This compels designers to moderate this degradation and to improve the lifetime of their circuits during the design phase. A simulation of aging becomes therefore essential to predict the performance degradation of the ICs due to temporal variations. Moreover, the introduction of new design techniques which consider reliability as a design constraint as important as speed, area, and power consumption, becomes more than necessary to warranty delivering reliable circuits and systems by adopting design for reliability (DFR) concept. In this prospect, we propose, on one hand, to migrate reliability analysis from device-level to a higher level of abstraction. This allows a better assessment of the induced degradation on the circuits’ performance. On the other hand, we propose a DFR approach to deign reliable circuits. For this PhD thesis we choose, to deal with NBTI, which is one of the most wear-out mechanisms shrinking the lifetime of deep submicron ICs. We present our NBTI circuit-level characterisation results, the implementation of our NBTI model on a commercial simulator. On the other hand, we present an NBTI mitigation approach based on transistor sizing we propose for designing robust 6T-SRAM cells