Reliability aware design of integrated circuits

Abstract

The striking advances in both computer-aided integrated circuit design and manufacturing technologies have paved the way for designing and manufacturing highly complex, high-performance chips integrating more than 100 million transistors into a few square millimeters of silicon. However, this high density has brought with it more challenges for IC designers in terms of their circuits reliability sign-off. In fact, due to the aggressive scaling, and to wear out effects, the electrical parameters of semiconductor devices are shifting over time, causing for ICs the failure to meet the specifications for which they were designed. However, a technology-based solution is not always feasible, mainly because semiconductor engineers usually focus on developing smaller, faster, and less energy-intensive transistors. This compels designers to moderate this degradation and to improve the lifetime of their circuits during the design phase. A simulation of aging becomes therefore essential to predict the performance degradation of the ICs due to temporal variations. Moreover, the introduction of new design techniques which consider reliability as a design constraint as important as speed, area, and power consumption, becomes more than necessary to warranty delivering reliable circuits and systems by adopting design for reliability (DFR) concept. In this prospect, we propose, on one hand, to migrate reliability analysis from device-level to a higher level of abstraction. This allows a better assessment of the induced degradation on the circuits’ performance. On the other hand, we propose a DFR approach to deign reliable circuits. For this PhD thesis we choose, to deal with NBTI, which is one of the most wear-out mechanisms shrinking the lifetime of deep submicron ICs. We present our NBTI circuit-level characterisation results, the implementation of our NBTI model on a commercial simulator. On the other hand, we present an NBTI mitigation approach based on transistor sizing we propose for designing robust 6T-SRAM cells