Implementation of a PC-Based Phasor measurement unit using LabVIEW
| dc.contributor.author | Benlakehal, Mohamed Elamine | |
| dc.contributor.author | Benlakehal, Mohamed Elamine | |
| dc.contributor.author | Benterkia, Mahdi | |
| dc.contributor.author | Zitouni, A. (Supervisor) | |
| dc.date.accessioned | 2022-06-22T09:38:45Z | |
| dc.date.available | 2022-06-22T09:38:45Z | |
| dc.date.issued | 2019 | |
| dc.description | 41 p. | en_US |
| dc.description.abstract | In this report, we will explain the different steps to construct a Phasor Measurements Unit. These steps include, building an anti-aliasing filter using Sallen-Key topology, demonstrating the synchronization process using GPS and PLL circuit and implementing the phasor estimation based on Discrete Fourier Transform DFT algorithm and LabVIEW. The overall system has been successfully tested by connecting it to real signals and three-phase voltages amplitudes and phases are extracted then plotted on the computer screen either in time domain or as phasor-vectors. | en_US |
| dc.description.sponsorship | Université M’Hamed BOUGARA de Boumerdes : Institut de génie electrique et electronique | en_US |
| dc.identifier.uri | https://dspace.univ-boumerdes.dz/handle/123456789/9614 | |
| dc.language.iso | en | en_US |
| dc.subject | Phasor estimation algorithm | en_US |
| dc.subject | Phasor measurement unit | en_US |
| dc.subject | DFT algorithm | en_US |
| dc.subject | Phased locked loop | en_US |
| dc.title | Implementation of a PC-Based Phasor measurement unit using LabVIEW | en_US |
| dc.type | Thesis | en_US |