FPGA assisted 3D iso-surface extraction

Abstract

Extracting Iso-surfaces from large 3D medical images is a very time consuming task. In this work we investigate if this process can be accelerated using a field programmable gate array (FPGA). A CPU-based isosurface extractor system has been implemented in several works using different approaches. One of the techniques by which we are interested is a modified Dividing Cubes algorithm based on an incremental search strategy for generating all points of the desired iso surface. This method involves a lot of iterative arithmetic calculations. We aim to use the FPGA to offload expensive, re-occurring calculations from the CPU by performing them on the FPGA and then transferring back the results to the computer before visualizing the generated 3D surface.