Deep neural network acceleration using Intel NIOS-II custom instructions.

Abstract

The rapid advancement of Artificia lIntelligence (AI ) hasled to its integration into various fields, including embedded systems, which present unique challenges due to constraint sin storage, power consumption, and the need for realtime execution. To optimize AI performance in these environments, we propose a hardware acceleration system. This system incorporates a floating point unit and lookup tables for Sigmoid and Leaky-ReLU activation functions, both designed using HDL and implemented on a Field Programmable Gate Array (FPGA) with the Nios II soft processor and its custom instructions. We tested this system on a Deep Neural Network (DNN) written in C and trained it multiple times with varying numbers of layers. The results were remarkable, with some networks experiencing performance improvements of over 60%. However, as the model’s complexity increased with additional layers, the acceleration benefi tdecreased, dropping to around 10% in the most complex scenarios. Despite this reduction in acceleration for highly complex models, our system remains reliable and efficient, demonstrating its potential for critic alreal-time embedded AIapplications.