A survey of GF (2m) multipliers on FPGA

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dc.contributor.authorHaichour, Amina Selma
dc.contributor.authorHamadouche, M’hamed
dc.date.accessioned2015-11-17T10:30:53Z
dc.date.available2015-11-17T10:30:53Z
dc.date.issued2015
dc.identifier.isbn978-147998200-4
dc.identifier.urihttps://dspace.univ-boumerdes.dz/handle/123456789/2442
dc.language.isoen_USen_US
dc.publisherIEEEen_US
dc.relation.ispartofseriesProceedings of 2014 9th International Design and Test Symposium, IDT/ (2014);pp. 215-218
dc.subjectFinite fieldsen_US
dc.subjectGF (2m) multiplicationen_US
dc.subjectField programmable gate arrays (FPGA)en_US
dc.subjectserial/sequential multiplieren_US
dc.subjectparallel/combinational multiplieren_US
dc.subjectHybrid multiplieren_US
dc.subjectDesignen_US
dc.subjectEconomic and social effectsen_US
dc.subjectHardwareen_US
dc.subjectReconfigurable architecturesen_US
dc.titleA survey of GF (2m) multipliers on FPGAen_US
dc.typeOtheren_US

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