Design and Evaluation of AES based Video Encryption/Decryption using FPGA-HPS

Abstract

The internet is an open and public system where information is send and received over shared wires and connections. Though we still exchange a lot of private data, things like credit card numbers, bank information, passwords, and emails. Especially during this pandemic, data exchange increased drastically due to the radical shift in the ways people communicate and engage with one another. Schools adopted online education, whereas employees are working from home. Virtual classrooms, webinars, and online meetings on video chat applications like zoom, google, and facebook have become the new normal of today’s world. Protecting and securing this tremendous amount of data in transit requires strong cryptographic algorithms. One of the most popular and widely used data protection schemes nowadays across the globe is The Advanced Encryption Algorithm (AES). However, security alone does not fulfil the requirements of modern systems, where speed is considered being an integral part of every design. The aim of our project is not to implement the AES-128 algorithm but to maximize its performance while using it in a video recording encryption/decryption application within the constrained embedded hardware of the Terasic DE10 Standard FPGA Board. Therefore, we have started our experiment by a pure software implementation of the AES-128 in C language, and then we created multiple design versions of the hybrid system that make use of the SoC HPS and FPGA. Finally, we implemented the fastest designs in a video encryption/decryption application. The results showed that the hybrid system has the advantage of faster execution by a factor of over 4 times when compared to the pure C implementation, which makes it a favorable choice in this type of applications on this platform.