FPGA implementation of stereo matching algorithm for depth estimation.

dc.contributor.authorYahia, Karim
dc.contributor.authorKhouas, Abdelhakim (Supervisor)
dc.date.accessioned2023-09-19T08:39:10Z
dc.date.available2023-09-19T08:39:10Z
dc.date.issued2022
dc.description48 p.en_US
dc.description.abstractComputer vision is an artificial intelligence branch developed for machines to perceive image and videos. It interprets visual data (pictures or videos) to extract information. One of its fundamental concepts is defined as stereo vision; used to estimate 3-D information of the scene. During depth estimation, a process denoted stereo matching is considered as the complex part; it requires a considerable amount of time to execute on a processor which prevents the systemto reach its minimum speed (30 frames per second). The proposed solution is moving the complex part of the system to hardware, since the latter is faster than software. To implement stereo matching, differenten_US
dc.description.sponsorshipUniversité M’hamed Bougara de Boumerdes : Institut de Genie Electrique et Electroniqueen_US
dc.identifier.urihttps://dspace.univ-boumerdes.dz/handle/123456789/12043
dc.language.isoenen_US
dc.subjectField Programmable Gate Array (FPGA)en_US
dc.subjectStereo matching algorithmen_US
dc.titleFPGA implementation of stereo matching algorithm for depth estimation.en_US
dc.typeThesisen_US

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