Improving the Detection Quality of the Clutter Map-Constant False Alarm Rate Detector in a Non-Homogeneous Environment

Abstract

This paper concerns the proposal of two innovative techniques for a clutter map-constant false alarm rate (CM-CFAR) detector. These techniques are called, respectively, adaptive linear combined-CM-CFAR (ALC-CM-CFAR), which operates without requiring any prior environmental knowledge, and knowledge-based systems ALC-CM-CFAR (KBSALC-CM-CFAR) that requires a previous environmental knowledge. The first technique, ALC-CM-CFAR, combines the performance of both detectors, cell averaging-CM-CFAR (CA-CM-CFAR) and ordered statistics-CM-CFAR (OS-CM-CFAR). In contrast, the second one, KBSALC-CM-CFAR, exploits the prior knowledge about the environment, KBS, considering both the Geographic Information System (GIS) and Kolmogorov–Smirnov (K–S) test as a knowledge source on the one hand, and the other hand, merging detection capabilities of CA-CM-CFAR and OS-CM-CFAR to build a robust detection system. This innovative approach aims to enhance the Nitzberg detector’s performance in detecting targets with low speeds and weak radar cross sections (RCS) across various environmental conditions. The performance of the proposed techniques was evaluated using Monte Carlo simulation using MATLAB software (MATLAB 8.6 R2015b). The results of the simulation reveal that the KBSALC-CM-CFAR surpasses all classical CM techniques; CA-CM-CFAR, OS-CM-CFAR, hybrid CM/L-CFAR, and CM/ordered data variability (ODV)-CFAR in terms of increasing the probability of detection (Pd) in different environment situations, especially in cases of non-homogeneity caused by interferences, slow, and weak RCS targets that persist in a cell map for several scans causing self-masking effect. The CM-CFAR technique was implemented on the field-programmable gate array (FPGA) processing board, and the process is run at a clock frequency of 50 MHz (execution time: 20 ns). After the simulation and execution of the algorithm, the execution time was evaluated at 5.636 ns. This is less than the running time of the FPGA board clock, which is equal to 20 ns, so processing takes place in real time. The consumption of hardware resources by the CM-CFAR algorithm is more than sufficient for implementation on the chosen FPGA (between 0.12 and 19.68%).