Sizing of the CMOS 6T-SRAM cell for NBTI ageing mitigation
| dc.contributor.author | Chenouf, Amel | |
| dc.contributor.author | Djezzar, Boualem | |
| dc.contributor.author | Bentarzi, Hamid | |
| dc.contributor.author | Benabdelmoumene, Abdelmadjid | |
| dc.date.accessioned | 2020-12-22T08:42:35Z | |
| dc.date.available | 2020-12-22T08:42:35Z | |
| dc.date.issued | 2020 | |
| dc.description.abstract | This study presents a negative bias temperature instability (NBTI) mitigation design technique for CMOS 6T-static random access memory (6T-SRAM) cells. The proposed approach is based on transistor sizing technique. It consists of sizing the nMOS access transistors of the cell to alleviate NBTI ageing occurring in its pMOS pull-up transistors threatening the cell stability. Once the access transistors are sized for a better hold static noise margin under NBTI, the other transistors of the 6T-SRAM cell could be properly sized for improved read stability and write-ability | en_US |
| dc.identifier.issn | 19729283 | |
| dc.identifier.other | DOI: 10.1049/iet-cds.2019.0307 | |
| dc.identifier.uri | https://ieeexplore.ieee.org/document/9139598 | |
| dc.identifier.uri | https://dspace.univ-boumerdes.dz/handle/123456789/5980 | |
| dc.language.iso | en | en_US |
| dc.publisher | IEEE | en_US |
| dc.relation.ispartofseries | IET Circuits, Devices and Systems, 14(4);PP. 555-561 | |
| dc.subject | Sizing | en_US |
| dc.subject | CMOS 6T-SRAM cell | en_US |
| dc.subject | NBTI ageing mitigation | en_US |
| dc.title | Sizing of the CMOS 6T-SRAM cell for NBTI ageing mitigation | en_US |
| dc.type | Article | en_US |