Evaluation of Hot Carrier Impact on Lateral- DMOS with LOCOS feature

Abstract

Hot carrier stress is evaluated on a laterally diffused MOSFET (LDMOS) by TCAD simulation. Thedevice under test is obtained from process simulation under a 1μm CMOS flow available at CDTA. The n- typetransistor uses the LOCOS (local oxidation of silicon) and single RESURF (reduced surface field) features.Using the trap degradation model, degradation over time and different biases, the shift of threshold voltage VTH,ON-state resistance RON, saturation current IDsat, and device lifetime are extracted. The shifts were foundto be manageable, they have a single process mechanism and are due to hot electrons in our case. But, flickernoise assessment under the same stress shows noticeable instabilities.