Analysis of the gate-to-channel capacitance variation for the tri-gate nanowire junctionless transistors
| dc.contributor.author | Smaani, Billel | |
| dc.contributor.author | Yakhelef, Yassine | |
| dc.contributor.author | Nafa, Fares | |
| dc.contributor.author | Salah, Mouhamed | |
| dc.date.accessioned | 2022-10-09T12:51:17Z | |
| dc.date.available | 2022-10-09T12:51:17Z | |
| dc.date.issued | 2021 | |
| dc.description.abstract | In this paper, the gate-to-channel capacitance variation for the tFlat-band voltageri-gate nanowire junctionless transistor (JLT) has been analyzed. It is based on the 2-D electrostatic numerical simulation realized using Silvaco-TCAD Software. The flat-band voltage and the threshold voltage are extracted trough the plotting of the derivative for the gate-to-channel capacitance versus the gate voltage. This plotting is performed for different values of the channel width and the channel height of the tri-gate JLT. Moreover, the physical effect of the back-gate biasing has been investigated | en_US |
| dc.identifier.uri | https://dspace.univ-boumerdes.dz/handle/123456789/10223 | |
| dc.language.iso | en | en_US |
| dc.relation.ispartofseries | Conference: GLOBAL CONFERENCE on ENGINEERING RESEARCH Project: Analyse of micro and nanostructures Silicium; | |
| dc.subject | Tri-gate junctionless nanowire | en_US |
| dc.subject | Gate-to-channel capacitance | en_US |
| dc.subject | Threshold voltage | en_US |
| dc.title | Analysis of the gate-to-channel capacitance variation for the tri-gate nanowire junctionless transistors | en_US |
| dc.type | Article | en_US |