Browsing by Author "Amiri, Amir Mohammad"

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Investigation of single cell delay and delay mismatch in ring oscillator based test structure
(2006) Zhou, Bo; Amiri, Amir Mohammad; Khouas, Abdelhakim
In previous work, we presented a test structure based on ring oscillator (RO) to measure single cell delay and delay mismatch, which can provide reliable information on intra-die and inter-die parameter variations. A delay cell of the configurable RO in the test structure considered for the computation technique consists of an inverter and a conducting transmission gate between adjacent cells. This paper will analyze the effects on delay cells of the transmission gates connecting to the output of inverters included in the active RO and investigate in depth delay mismatch in this RO based test structure. Monte Carlo simulation results reveal that the computation technique is applicable to derive delay mismatch between delay cells. A large number of post-layout simulations for different layout structures with different number of cells and different transistor sizes have been performed to analyze delay mismatch related to interconnect and device parameter variations
Low Dead Time, Multi-hit FPGA-Based Time-to-Digital Converter
(IEEE, 2006) Amiri, Amir Mohammad; Boukadoum, Mounir; Khouas, Abdelhakim
This paper presents improvements on a novel FPGAbased multi-hit Time-to-Digital Converter (TDC) to measure time intervals with a resolution of 100ps and a variable dynamic range controlled by a binary coarse counter. We use a matrix topology to provide a two-level resolution, aiming to minimize the overall measurement time. The conventional dead time is eliminated by the continuous detection and processing of data by two delay matrices operating in parallel. A back-resetting scheme eliminates the erroneous multi-detection of an event along matrix tap lines. The circuit was tested on a XILINX SPARTAN-3 FPGA platform.
A Multihit Time-to-Digital Converter Architecture on FPGA
(IEEE, 2009) Amiri, Amir Mohammad; Boukadoum, Mounir; Khouas, Abdelhakim
We present a multihit time-to-digital converter (TDC) architecture implemented in a field-programmable gate array (FPGA) with minimized timing overhead. The TDC circuit provides two-level fine-time interpolation. The fine interpolator is a matrix of Vernier delay cells interconnected in a topology to provide two propagation paths for the incoming data pulse. Two methods of calibration are presented to estimate the component delays. The TDC circuit achieves time measurements with a resolution of 75 ps with an average precision of ~ 300 ps and is capable of detecting incoming pulses at a distance of 7.5 ns or more from each other
On the Timing Uncertainty in Delay-Line-based Time Measurement Applications Targeting FPGAs
(IEEE, 2007) Amiri, Amir Mohammad; Khouas, Abdelhakim; Boukadoum, Mounir
this paper addresses important performance issues in delay-line-based timing applications targeting FPGA devices. The circuit under test is a TDC circuit implemented on a low-cost FPGA from XILINX. Various performance limitations such as uncertainty and non-uniformity in cell delays are described and corresponding optimization and improvement suggestions are made. Experimental results were obtained using ring oscillator-based test structures to inspect intra-die delay mismatches along the target FPGA’s surface
Pseudorandom stimuli generation for testing time-to-digital converters on an FPGA
(IEEE, 2009) Amiri, Amir Mohammad; Khouas, Abdelhakim; Boukadoum, Mounir
This paper presents a pulse generator circuit that produces a stream of pulses at pseudorandom time intervals. The proposed circuit may serve as a stimulus generator for code density testing of time-to-digital converters (TDCs). The functional behavior of the circuit was first investigated with a software model coded in C ++. The software simulation showed that the interpulse intervals only uniformly cover their domain at a given resolution if the greatest common divisor between the intervals and the observation window is 1 with respect to a common reference clock. In a second step, the circuit was implemented in hardware using very high-speed integrated circuit (VHSIC) hardware description language (VHDL) and tested on a Xilinx Spartan-3 field-programmable gate array (FPGA) platform. The pulse density histograms obtained from the software and hardware test cases show pulse distributions with nonlinearity values within one least significant bit (LSB). In the end, the circuit was used as a stimulus generator for code density testing of a TDC circuit on an FPGA