Browsing by Author "Houadef, Ali"

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    Detailed total ionizing dose effects on LDMOS transistors
    (Springer, 2022) Houadef, Ali; Djezzar, Boualem
    The degradation of lateral double-diffused MOSFETs (LDMOS) due to total ionizing dose (TID) effects is examined in this paper using physics-based 2D TCAD simulations. The devices under test (DUTs) are built with a single reduced surface field (single-RESURF) structure and local oxidation of silicon (LOCOS) field oxide. The device structure was chosen for its topological simplicity in comparison to other modern LDMOS transistors to explore the impact of gamma radiation on small-AC and RF behavior. The results demonstrate fundamental differences between n-type (nLDMOS) and the p-type (pLDMOS) parameter shifts. Due to the distinct damage location in the pLDMOS, which is mainly the drift region, TID augments the values of the various parasitic capacitances. However, in the nLDMOS, TID reduced those values, especially the gate capacitance overshoot, as the degradation happens in the channel region and the bird's beak mostly. Consequently, the RF response and stability of the devices will differ. In addition, we present new research opportunities for TID effects on LDMOS transistors in particular, but also for radiation studies in general
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    Evaluation of Hot Carrier Impact on Lateral- DMOS with LOCOS feature
    (Université M'hamed Bougara de Boumerdès : Laboratory of Signals and Systems, 2021) Houadef, Ali; Djezzar, Boualem
    Hot carrier stress is evaluated on a laterally diffused MOSFET (LDMOS) by TCAD simulation. Thedevice under test is obtained from process simulation under a 1μm CMOS flow available at CDTA. The n- typetransistor uses the LOCOS (local oxidation of silicon) and single RESURF (reduced surface field) features.Using the trap degradation model, degradation over time and different biases, the shift of threshold voltage VTH,ON-state resistance RON, saturation current IDsat, and device lifetime are extracted. The shifts were foundto be manageable, they have a single process mechanism and are due to hot electrons in our case. But, flickernoise assessment under the same stress shows noticeable instabilities.
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    HCI degradation of LOCOS-based LDMOS transistor fabricated by 1 μ m CMOS process
    (IEEE, 2020) Houadef, Ali; Djezzar, Boualem
    Physically based device simulation of hot carrier injection (HCI) degradation is performed. The device under test is a LOCOS (local oxidation of silicon) based, single RESURF (reduced surface field), LDMOS (laterally diffused MOSFET). The transistor is obtained from process simulation, based on 1 μ m CMOS technology available at CDTA. Using the trap degradation model, degradation over time and different biases, the shift of threshold voltage Δ VTH, ON-state resistance (Δ RON, saturation current (Δ IDSat) and device lifetime are extracted. In addition, a quasi-static RF characterization is done for different stress times with a particular focus on flicker noise. The results show that DC parameter shifts are linear but still manageable. However, under RF regimes significant instabilities are encountered
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    Hot carrier degradation in Triple-RESURF LDMOS with Trenched-Gate
    (IEEE, 2021) Houadef, Ali; Djezzar, B.
    This work investigates by TCAD simulation the impact of hot carrier degradation (HCD) in an nLDMOS that uses many topological features. The trenched gate and the triple-RESURF used to optimally reduce the device on-resistance (RON) , triggers DC shifts that easily surpass 10%. We show that using such topologies implicates a narrower safe operating area (SOA)
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    Process and performance optimization of Triple-RESURF LDMOS with Trenched-Gate
    (Wiley, 2021) Houadef, Ali; Djezzar, Boualem
    In this article, we investigate by TCAD simulation, the combination triple reduced surface field (triple-RESURF) and trenched-gate to design an n-type laterally diffused metal-oxide-semiconductor (LDMOS) transistor with high performance. While similar structures reported in the literature, on the one hand, use either the triple-RESURF or trenched-gate at once, on the other hand, those features require at least one additional mask each. We have been able to achieve both features in one transistor with only eight masks at the front-end of line (FEOL), and one less annealing. Therefore, our proposition will be cheaper and provide better performance. The structure is obtained by re-organizing the process steps, re-using other existing masks, and exploiting positive and negative photoresist photolithography. The resulting specific on-state resistance (RON,SP) is 94 mΩmm2, and the breakdown voltage (BV) is 71 V. But, most importantly a high transconductance (gm) at high gate voltages, with acceptable off-state leakage current (Ioff), which translates into better RF performance overall than what is reported in the literature. The maximum oscillation frequency (fMAX) and cut-off frequency (fT) could reach up to 76 and 43 GHz, respectively. Our device targets fully integrated IoT ASICs that require power amplifiers