Browsing by Author "Khouas, Abdelhakim"

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Accelerating Stereo Matching on Mutlicore ARM Platform
(IEEE, 2020) Saidi, Taki Eddine; Khouas, Abdelhakim; Abbes, Amira
Stereo vision is a well-known technique in computervision used to acquire the 3D depth information of a scenefrom two or more 2D images. One of the main issues with anystereo vision system is how to make a good trade off betweenthe processing speed and the quality of the disparity map. Thisissue can be resolved through the use of dedicated hardwareplatforms, like Field Programmable Gate Arrays and GraphicalProcessing Units, which are considered as expensive solutions.In this work, the challenge of accelerating stereo matching onlow cost multicore platforms is tackled. We present a novelsoftware implementation of a sparse Rank algorithm, that uses amodified Sum of Absolute Differences 1D box filtering algorithmin the correlation stage. Consequently, we reduce the numberof computations and memory space needed for computing thedisparity map. The system is implemented on a multicoreAdvanced Risc Machine platform (ODROID XU4). Experimentalresults show that the system is capable of achieveing a processingspeed of 59 Frames Per Second for images of size320×240pixelswith a disparity range of 20 pixels. Furthermore, the sparse Rankstructure does not affect significantly the overall quality of thedisparity map.
Accurate testability analysis based-on multi-frequency test generation and a new testability metric
(IEEE, 2008) Abderrahman, A.; Savaria, Yvon; Khouas, Abdelhakim; Sawan, Mohamad
The effectiveness of testing the analog part of mixed-signal circuits impacts their overall manufacturing cost. Therefore, it is important to have accurate metrics to estimate fault coverage and to precisely measure the test quality. In this paper, we propose an accurate testability analysis based on multi-frequency test pattern generation and a new testability measure called the parameter fault coverage (PFC) that takes into account the continuous characteristic of the parametric faults spectrum and masking effect of process variations. This new analog test metric allows accurately measuring analog test quality and enables taking better decisions regarding the use of design for testability (DFT) techniques. Therefore, poor product test quality and unnecessary design modifications, which may be caused by incorrect fault coverage estimates, can be avoided
Analog Fault Detection based on Statistical Analysis
(Hal, 2000) Khouas, Abdelhakim; Derieux, Anne
In analog circuits, process variations result in physical parameter variations. Simulated values must then be considered with there tolerance intervals. Consequently, contrarily to digital circuits where the outputs are either '0' or '1' such that we can decide without ambiguity whether a fault is detectable or not, for analog circuits the fault detectability is a vague problem as the fault can either be completely detectable, partially detectable or completely undetectable which makes it very diOEcult to take a decision. In order to solve this decision problem, we have introduced the probability to detect fault (PDF) function which allows to formalize the problem of analog fault detection under parameter variations
Analysis of DC simulation convergence of nonlinear analog circuits with initial solution
(IEEE, 2005) Morneau, Michel; Khouas, Abdelhakim
An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware
(IEEE, 2019) Guettatfi, Zakarya; Platzner, Marco; Kermia, Omar; Khouas, Abdelhakim
Executing real-time tasks on FPGAs involves interdependent placement and scheduling problems. Most presented approaches model tasks as rectangles and allow for placing tasks anywhere on the FPGA. Such models are, however, not supported by commercial technology and tool flows. We present a new approach for mapping periodic real-time tasks to FPGAs based on micro slots, which are aggregated to reconfigurable slots that can accommodate a task at a time. This model enables us to leverage existing real-time scheduling results, but also poses new problems of reconfigurable slot creation and layout generation and, most importantly, lends itself to a practical realization. We discuss our overall approach, detail heuristics for reconfigurable slot creation and layout generation, and present simulation experiments
Blind source separation based phase estimator for carrier synchronization of high-order QAM signals
(IEEE, 2015) Chouiha, Mustapha; Khouas, Abdelhakim; Belouchrani, Adel; Baudoin, Geneviève
In this paper, a new carrier synchronization loop for high-order QAM signals has been proposed in which a blind source separation algorithm for carrier phase tracking is used as phase estimator in feed-back configuration. When used for large constellation schemes, simulations show that the proposed solution achieves better phase tracking and improves performance of the carrier phase tracking loop in terms of bit error rate versus energy per bit to noise ratio (BER vs Eb/N0) comparing to the descent algorithm and to Decision Directed synchronizer
A complete spurs distribution model for direct digital period synthesizers
(IEEE, 2005) Salomon, Max-Elie; Khouas, Abdelhakim; Savaria, Yvon
This paper presents a new, fully automated algorithm modeling the spurious frequencies in direct digital period synthesizers (DDPS). DDPS is a frequency synthesis technique that combines the speed and low jitter of a delay-locked-loop-based frequency multiplier, with the ability to digitally control the frequency. The algorithm is based on an analysis of the periodicity of the output signal produced by a DDPS circuit on which a time-domain Fourier analysis is performed. The resulting spectrum reflects two major known sources of spurious frequencies in DDPS: accumulator output truncation and delay line cell mismatch. Comparisons with results obtained from time-consuming simulations performed with SIMULINK and processed by FFT were performed to validate the model. An efficient implementation of the proposed algorithm allows comparing many different operating conditions that could not be analyzed with the SIMULINK model due to excessive processing time
Elliptic curve digital signature system implementationon embedded ARM processor.
(Université M’hamed Bougara de Boumerdes : Institut de Genie Electrique et Electronique, 2023) Bourahla, Amina; Nebhi, Lynda; Khouas, Abdelhakim
Elliptic Curve Digital Signature Algorithm (ECDSA) is a widely-used cryptographic algorithm that verifie sth eauthenticit yo fdigita lmessages.Th emai nadvantag eo fECDS Aove rother signature algorithms is requiring smaller key sizes to achieve the same level of security. The smaller size of the key results in faster operations due to its employment in the most computationally heavy part of the ECDSA algorithm: the Elliptic Curve (EC) Point Multiplication (PM). Therefore, it is a target for optimization to achieve better speed, memory consumption, energy dissipation and security. Some approaches rely on hardware support such as the use of parallelism and more memory. Others, depend on a more efficie ntu se of ECarithmet ic as EC PM isbui lt onEC operations: Addition (ADD), and Doubling (DBL). The Radix- 2 w method for EC PM relies on the recoding of the scalar with fewer nonzero digits in a w-bit window serving to reduce the cost in terms of ADD operations used. This project focuses on the implementation of ECDSA using the Radix- 2 w method for EC point multiplication (PM) and Double Point Multiplication (DPM); DPM is the sum of two EC PMs. This implementation is realized in the context of national institute of standards and technology recommended binary ECs, and serves as proof of concept for the Radix- 2 w multiplication methods. The Zynq Evaluation and Development Board’s processing system (PS) is used for the implementation as it allows for later integration of PL blocks for the Radix- 2 w multiplication making up a hardware/software solution. The project was carried out in three parts. First, the Radix- 2 w multiplication methods were implemented on computer, and their functionality validated. Subsequently, they were tested to reveal a 58.63% improvement in the cost of the Radix- 2 w EC PM method over the binary EC PM method in terms of ADDs, and a 47.509% improvement in the cost (in terms of ADDs) for the Radix- 2 w EC DPM method over the binary EC DPM method. Second, the ECDSA protocol was implemented on computer, along with an encryption protocol to complement the security provided by the signature (authentication and non repudiation). The reason behind this is that signature algorithms do not provide confidentiality. Thus, for the purpose of encryption, El-Gamal algorithm was used for its compatibility with ECs. Third and finally, the complet eECDSA/El-Gama encryption protocol using Radix- 2w methods for multiplication was adapted to the zedboard PS. This project resulted in the successful signature generation/verificatio nan dmessag eencryption/decryptio nbetwee nth eboar dan d acomputer using Radix- 2 w methods for multiplication.
Fault Simulation for Analog Circuits Under Parameter Variations
(2000) Khouas, Abdelhakim; Derieux, Anne
Analog integrated circuit testing and diagnosis is a very challenging problem. The inaccuracy of measurements, the infinite domain of possible values and the parameter deviations are among the major difficulties. During the process of optimizing production tests, Monte Carlo simulation is often needed due to parameter variations, but because of its expensive computational cost, it becomes the bottleneck of such a process. This paper describes a new technique to reduce the number of simulations required during analog fault simulation. This leads to the optimization of production tests subjected to parameter variations. In Section 1 a review of the state of the art is presented, Section 2 introduces the algorithm and describes the methodology of our approach. The results on CMOS 2-stage opamp and Fifth-order Low-pass switched-capacitor Filter are given in Sections 3 and conclusions in Section 4
FDP: fault detection probability function for analog circuits
(IEEE, 2001) Khouas, Abdelhakim; Derieux, A.
In analog integrated circuits, process variations result in physical parameter variations. Simulated performance values must then be considered with their tolerance intervals. Consequently, contrarily to digital circuits where the outputs are either '0 or ' 1' such that we can decide without ambiguity whether a fault is detectable or not, for analog circuits fault detectability is still a vague problem since the fault can either be completely detectable, partially detectable or completely undetectable which makes it very difficult to take a decision. In order to solve this decision problem, we have introduced the fault detection probability (FDP) function which allows to formalize the problem of analog fault detection subjected to parameter variations
FPGA design of a real-time obstacle detection system using stereovision
(IEEE, 2012) Bendaoudi, Hamza; Khouas, Abdelhakim; Cherki, Brahim
Obstacle detection using stereovision is an important issue in intelligent vehicle and robot navigation, especially for the Advanced Driver Assistance Systems. This paper presents real-time obstacle detection system designed and implemented on single Field Programmable Gate Array (FPGA). The proposed hardware architecture combines stereo vision algorithms to compute the disparity map, V-disparity image, and Hough transform for obstacle detection. Considering the particular aspect of the V-disparity image and the real-time constraint, the Hough transform is only applied to detect the obstacles corresponding lines. The proposed system was tested in indoor environment using Virtex-II FPGA based prototyping board. For 640×480 pixels images, the proposed system can treat up to 180 frames/s when running at full rate, with a minimum detection time of 5.5 ms
FPGA implementation of the V-disparity based obstacles detection approach
(IEEE, 2013) Irki, Zohir; Bendaoudi, Hamza; Devy, Michel; Khouas, Abdelhakim
In this paper we present an implementation of the whole V-disparity obstacles detection approach on an FPGA component. This approach is based on the use of stereoscopic images for the construction of an image called the V-disparity image from which obstacles can be easily extracted using a particular Hough transform. FPGA represents a good alternative for the use of the approach on an embedded system. The implementation of the approach on an FPGA component requires parallelizing all its steps which are the stereoscopic matching, the V-disparity image construction and obstacles extraction using a unidirectional Hough transform. These steps have been described with VHDL language using the ISE 9.2 software. Finally, the entire approach has been implemented on a Virtex-II type XC2V1000 FG456-4 placed on an RC200 board
FPGA-based real-time implementation of distributed system CA-CFAR and Clutter MAP-CFAR with noncoherent integration for radar detection
(IEEE, 2012) Benseddik, Houssem Eddine; Cherki, Brahim; Hamadouche, M'hamed; Khouas, Abdelhakim
In this work, we propose real time implementation approaches of distributed Constant False Alarm Rate (CFAR) detection with noncoherent integration. The Cell Averaging (CA-CFAR) and Clutter MAP (CMAP-CFAR) detectors are employed as local detectors. The proposed architecture shows that it can be implemented with the advantages of a parallel structure and allows an important optimization of the required FPGA hardware resources utilization. The structure has been implemented using a Virtex-II XC2V1000-4FG456C FPGA board. The FPGA implementation results are presented and discussed
Hardware design and FPGA implementation for road plane extraction based on V-disparity approach
(IEEE, 2015) Benacer, I.; Hamissi, A.; Khouas, Abdelhakim
Hardware Design and FPGA Implementation for Road Plane Extraction Based on V-disparity Approach
(2015) Benacer, Imad; Hamissi, Aicha; Khouas, Abdelhakim
Accurate and real-time free space and obstacles detection is a task of great interest to the navigation of mobile robots, and the integration to existing vehicle's safety systems. This paper presents a novel approach for road plane extraction, free space and obstacles discrimination using stereovision. The estimated road profile from V-disparity images allows robust extraction of the road features from pixels classification of the disparity map. The proposed hardware architecture combines parallel processing with dedicated and optimized modules to reduce logic resource utilization, and accelerate processing time. This architecture is implemented on Cyclone IV E FPGA based prototyping board, and tested using real stereoscopic images of different environments. Experimental results demonstrate the efficiency and accuracy of the proposed method. The implemented system can treat up to 490 and 122 frames/s for stereoscopic images of 320×240 and 640×480 pixels respectively
Investigation of single cell delay and delay mismatch in ring oscillator based test structure
(2006) Zhou, Bo; Amiri, Amir Mohammad; Khouas, Abdelhakim
In previous work, we presented a test structure based on ring oscillator (RO) to measure single cell delay and delay mismatch, which can provide reliable information on intra-die and inter-die parameter variations. A delay cell of the configurable RO in the test structure considered for the computation technique consists of an inverter and a conducting transmission gate between adjacent cells. This paper will analyze the effects on delay cells of the transmission gates connecting to the output of inverters included in the active RO and investigate in depth delay mismatch in this RO based test structure. Monte Carlo simulation results reveal that the computation technique is applicable to derive delay mismatch between delay cells. A large number of post-layout simulations for different layout structures with different number of cells and different transistor sizes have been performed to analyze delay mismatch related to interconnect and device parameter variations
Low Dead Time, Multi-hit FPGA-Based Time-to-Digital Converter
(IEEE, 2006) Amiri, Amir Mohammad; Boukadoum, Mounir; Khouas, Abdelhakim
This paper presents improvements on a novel FPGAbased multi-hit Time-to-Digital Converter (TDC) to measure time intervals with a resolution of 100ps and a variable dynamic range controlled by a binary coarse counter. We use a matrix topology to provide a two-level resolution, aiming to minimize the overall measurement time. The conventional dead time is eliminated by the continuous detection and processing of data by two delay matrices operating in parallel. A back-resetting scheme eliminates the erroneous multi-detection of an event along matrix tap lines. The circuit was tested on a XILINX SPARTAN-3 FPGA platform.
Measurement of delay mismatch due to process variations by means of modified ring oscillators
(IEEE, 2005) Zhou, B.; Khouas, Abdelhakim
A novel and effective test circuit to measure cell-tocell delay mismatch due to process variations is presented. A fully digital control circuit that efficiently realizes the technique is also described. The proposed test structure is realized by a series of modified ring oscillators that minimize factors of inaccuracy. The results of a simulation using 0.18μm CMOS technology show the feasibility of the technique. This test structure can be beneficial in thoroughly characterizing the effects of systematical process variations inside the chip.
Methodology for Fast and Accurate Analog Production Test
(1999) Khouas, Abdelhakim; Derieux, Anne
This paper describes a new technique to reduce the number of simulations required during analog fault simulation. The method takes into account process parameter variations and aims to reduce the number of the computational expensive Monte Carlo simulations often required during analog fault simulation. In section I a review of the state of the art.
Modeling Efficient Inductive Power Transfer Required To Supply Implantable Devices
(2005) Sehil, Mohamed; Sawan, Mohamad; Khouas, Abdelhakim
This paper presents a model for inductively coupled links with an integrated receiver on silicon. To be accurate, this model includes losses related to the integration of the receiver The modelling technique of the receiver coil has been verified using Agilent Momentum Electro-Magnetic simulations. This comprehensive model is employed to obtain maximum power efficiency by performing a discrete optimization of the geometric dimensions of the link coils. The optimized link can deliver 50mW to a visual cortical stimulator and monitoring devices with an efficiency of 21% at a distance of 1cm. The receiver has 4mm of diameter