Browsing by Author "Savaria, Yvon"

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Accurate testability analysis based-on multi-frequency test generation and a new testability metric
(IEEE, 2008) Abderrahman, A.; Savaria, Yvon; Khouas, Abdelhakim; Sawan, Mohamad
The effectiveness of testing the analog part of mixed-signal circuits impacts their overall manufacturing cost. Therefore, it is important to have accurate metrics to estimate fault coverage and to precisely measure the test quality. In this paper, we propose an accurate testability analysis based on multi-frequency test pattern generation and a new testability measure called the parameter fault coverage (PFC) that takes into account the continuous characteristic of the parametric faults spectrum and masking effect of process variations. This new analog test metric allows accurately measuring analog test quality and enables taking better decisions regarding the use of design for testability (DFT) techniques. Therefore, poor product test quality and unnecessary design modifications, which may be caused by incorrect fault coverage estimates, can be avoided
A complete spurs distribution model for direct digital period synthesizers
(IEEE, 2005) Salomon, Max-Elie; Khouas, Abdelhakim; Savaria, Yvon
This paper presents a new, fully automated algorithm modeling the spurious frequencies in direct digital period synthesizers (DDPS). DDPS is a frequency synthesis technique that combines the speed and low jitter of a delay-locked-loop-based frequency multiplier, with the ability to digitally control the frequency. The algorithm is based on an analysis of the periodicity of the output signal produced by a DDPS circuit on which a time-domain Fourier analysis is performed. The resulting spectrum reflects two major known sources of spurious frequencies in DDPS: accumulator output truncation and delay line cell mismatch. Comparisons with results obtained from time-consuming simulations performed with SIMULINK and processed by FFT were performed to validate the model. An efficient implementation of the proposed algorithm allows comparing many different operating conditions that could not be analyzed with the SIMULINK model due to excessive processing time
New Analog Test Metrics Based on Probabilistic and Deterministic Combination Approaches
(IEEE, 2008) Abderrahman, A.; Sawan, Mohamad; Savaria, Yvon; Khouas, Abdelhakim
The continuous characteristic of the parametric faults spectrum, the process variations and their masking effects are major difficulties limiting the development of efficient test generation for parametric faults. Moreover, there is a need for accurate test metrics to quantify the quality of a test set and to determine whether the testability is adequate. An analog test metric called parameter fault coverage (PFC) was recently introduced by the authors. The PFC metric takes into account the combination of the above major difficulties. In this paper, we consider parametric faults caused by the increased variance in device parameters. We introduce two novel metrics: one is called guaranteed parameter fault coverage (GPFC), which is the guaranteed lower bound of the PFC, and the other one is called partial parameter fault coverage (PPFC), which is the probabilistic component of the PFC. We combine the deterministic metric GPFC and the probabilistic metric PPFC to produce a PFC metric that enables accurately measuring the analog test quality and allows precisely measuring testability, thus avoiding the drawbacks of incorrect decisions regarding the use of design for testability (DFT) techniques. Also, we show that when DFT is used to improve circuit testability, PFC becomes dominated by the deterministic component GPFC, while the probabilistic component PPFC is minimized. This paper demonstrates the effectiveness of our approach on an illustrative example
Spur Model for a Fixed-Frequency Signal Subject to Periodic Jitter
(IEEE, 2008) Salomon, Max-Elie; Izouggaghen, Badre; Khouas, Abdelhakim; Savaria, Yvon
This paper presents an automated algorithm that is capable of predicting both the location and magnitude of spurs that are caused by different sources of jitter on a periodic signal. A practical circuit that produces this kind of jittered periodic signal is the direct digital period synthesis (DDPS) circuit that can be used as a flexible clock source for various applications such as adjusting a sampling rate in a measurement and signal processing. Points of interest with clocks that are subject to periodic perturbations are their spectral purity and jitter characteristics. Our algorithm is applied to the DDPS to greatly reduce the simulation time that is needed to accurately compute the spectrum of the signal and its spurious frequency content. The method is used to explore how the operating parameters of the DDPS influence the spectral purity of its output. The generic analysis method that has been used in this paper can be transposed to fractional- N synthesizers, delay-line-based direct digital synthesizers, or serializers
Spurs modeling in direct digital period synthesizers related to phase accumulator truncation
(IEEE, 2005) Izouggaghen, Badre; Khouas, Abdelhakim; Savaria, Yvon
This paper presents an analytic model of the spurious noise frequencies in Direct Digital Period Synthesizer (DDPS) due to phase accumulator truncation. DDPS is a new technique for frequency synthesis that takes advantage of the speed and low jitter of a delay-lockedloop- based frequency multipliers and the ability to digitally control the frequency from the direct digital synthesis technique DDS [1-2]. The most important source of spurious noise frequencies in a DDPS circuit is the truncation of the output of its phase accumulator. Computing spectral analysis of DDPS circuit is a CPU time consuming task. Based on series of analytic calculations, a general and simple mathematical formula of the location of spurious frequencies and their magnitudes is predicted. This formula will help designers analyze and develop new DDPS circuits faster