Communications Internationales

Permanent URI for this collectionhttps://dspace.univ-boumerdes.dz/handle/123456789/11

Browse

Author: search.filters.author.Khouas, Abdelhakim

Search Results

Now showing 1 - 10 of 26
  • No Thumbnail Available
    Item
    Speed-up of high accuracy analog test stimulus optimization
    (1999) Khouas, Abdelhakim; Derieux, Anne
    Analog integrated circuit testing and diagnosis is a very challenging problem. The inaccuracy of measurements, the infinite domain of possible values and the parameter deviations are among the major difficulties. During the process of optimizing production tests, Monte Carlo simulation is often needed due to parameter variations, but because of its...
  • No Thumbnail Available
    Item
    FPGA-based real-time implementation of distributed system CA-CFAR and Clutter MAP-CFAR with noncoherent integration for radar detection
    (IEEE, 2012) Benseddik, Houssem Eddine; Cherki, Brahim; Hamadouche, M'hamed; Khouas, Abdelhakim
    In this work, we propose real time implementation approaches of distributed Constant False Alarm Rate (CFAR) detection with noncoherent integration. The Cell Averaging (CA-CFAR) and Clutter MAP (CMAP-CFAR) detectors are employed as local detectors. The proposed architecture shows that it can be implemented with the advantages of a parallel structure and allows an important optimization of the required FPGA hardware resources utilization. The structure has been implemented using a Virtex-II XC2V1000-4FG456C FPGA board. The FPGA implementation results are presented and discussed
  • No Thumbnail Available
    Item
    Hardware Design and FPGA Implementation for Road Plane Extraction Based on V-disparity Approach
    (2015) Benacer, Imad; Hamissi, Aicha; Khouas, Abdelhakim
    Accurate and real-time free space and obstacles detection is a task of great interest to the navigation of mobile robots, and the integration to existing vehicle's safety systems. This paper presents a novel approach for road plane extraction, free space and obstacles discrimination using stereovision. The estimated road profile from V-disparity images allows robust extraction of the road features from pixels classification of the disparity map. The proposed hardware architecture combines parallel processing with dedicated and optimized modules to reduce logic resource utilization, and accelerate processing time. This architecture is implemented on Cyclone IV E FPGA based prototyping board, and tested using real stereoscopic images of different environments. Experimental results demonstrate the efficiency and accuracy of the proposed method. The implemented system can treat up to 490 and 122 frames/s for stereoscopic images of 320×240 and 640×480 pixels respectively
  • No Thumbnail Available
    Item
    Blind source separation based phase estimator for carrier synchronization of high-order QAM signals
    (IEEE, 2015) Chouiha, Mustapha; Khouas, Abdelhakim; Belouchrani, Adel; Baudoin, Geneviève
    In this paper, a new carrier synchronization loop for high-order QAM signals has been proposed in which a blind source separation algorithm for carrier phase tracking is used as phase estimator in feed-back configuration. When used for large constellation schemes, simulations show that the proposed solution achieves better phase tracking and improves performance of the carrier phase tracking loop in terms of bit error rate versus energy per bit to noise ratio (BER vs Eb/N0) comparing to the descent algorithm and to Decision Directed synchronizer
  • No Thumbnail Available
    Item
    An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware
    (IEEE, 2019) Guettatfi, Zakarya; Platzner, Marco; Kermia, Omar; Khouas, Abdelhakim
    Executing real-time tasks on FPGAs involves interdependent placement and scheduling problems. Most presented approaches model tasks as rectangles and allow for placing tasks anywhere on the FPGA. Such models are, however, not supported by commercial technology and tool flows. We present a new approach for mapping periodic real-time tasks to FPGAs based on micro slots, which are aggregated to reconfigurable slots that can accommodate a task at a time. This model enables us to leverage existing real-time scheduling results, but also poses new problems of reconfigurable slot creation and layout generation and, most importantly, lends itself to a practical realization. We discuss our overall approach, detail heuristics for reconfigurable slot creation and layout generation, and present simulation experiments
  • No Thumbnail Available
    Item
    Accelerating Stereo Matching on Mutlicore ARM Platform
    (IEEE, 2020) Saidi, Taki Eddine; Khouas, Abdelhakim; Abbes, Amira
    Stereo vision is a well-known technique in computervision used to acquire the 3D depth information of a scenefrom two or more 2D images. One of the main issues with anystereo vision system is how to make a good trade off betweenthe processing speed and the quality of the disparity map. Thisissue can be resolved through the use of dedicated hardwareplatforms, like Field Programmable Gate Arrays and GraphicalProcessing Units, which are considered as expensive solutions.In this work, the challenge of accelerating stereo matching onlow cost multicore platforms is tackled. We present a novelsoftware implementation of a sparse Rank algorithm, that uses amodified Sum of Absolute Differences 1D box filtering algorithmin the correlation stage. Consequently, we reduce the numberof computations and memory space needed for computing thedisparity map. The system is implemented on a multicoreAdvanced Risc Machine platform (ODROID XU4). Experimentalresults show that the system is capable of achieveing a processingspeed of 59 Frames Per Second for images of size320×240pixelswith a disparity range of 20 pixels. Furthermore, the sparse Rankstructure does not affect significantly the overall quality of thedisparity map.
  • No Thumbnail Available
    Item
  • No Thumbnail Available
    Item
    Over effective hard real-time hardware tasks scheduling and allocation
    (IEEE, 2015) Guettatfi, Zakarya; Kermia, Omar; Khouas, Abdelhakim
  • No Thumbnail Available
    Item
    Fault Simulation for Analog Circuits Under Parameter Variations
    (2000) Khouas, Abdelhakim; Derieux, Anne
    Analog integrated circuit testing and diagnosis is a very challenging problem. The inaccuracy of measurements, the infinite domain of possible values and the parameter deviations are among the major difficulties. During the process of optimizing production tests, Monte Carlo simulation is often needed due to parameter variations, but because of its expensive computational cost, it becomes the bottleneck of such a process. This paper describes a new technique to reduce the number of simulations required during analog fault simulation. This leads to the optimization of production tests subjected to parameter variations. In Section 1 a review of the state of the art is presented, Section 2 introduces the algorithm and describes the methodology of our approach. The results on CMOS 2-stage opamp and Fifth-order Low-pass switched-capacitor Filter are given in Sections 3 and conclusions in Section 4
  • No Thumbnail Available
    Item
    FDP: fault detection probability function for analog circuits
    (IEEE, 2001) Khouas, Abdelhakim; Derieux, A.
    In analog integrated circuits, process variations result in physical parameter variations. Simulated performance values must then be considered with their tolerance intervals. Consequently, contrarily to digital circuits where the outputs are either '0 or ' 1' such that we can decide without ambiguity whether a fault is detectable or not, for analog circuits fault detectability is still a vague problem since the fault can either be completely detectable, partially detectable or completely undetectable which makes it very difficult to take a decision. In order to solve this decision problem, we have introduced the fault detection probability (FDP) function which allows to formalize the problem of analog fault detection subjected to parameter variations