Communications Internationales

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Influence of surface roughness on the deuterium inventoryof ASDEX-UPGRADE divertor tiles
(1998) Hildebrandt, D.; Akbi, Mohamed; Jüttner, B.; Schneider, W.
The gas inventory of divertor target tiles used in ASDEX-UPGRADE has been analyzed by thermodesorption spectrometry (TDS°. desorbed gaseous molecules have been measured by heating up complete and cut divertor tiles. the largest samplrs '80X80mm2)could be heated up to temperatures of 1500 K and smaller ones to even higher temperatures.in addition, surface analysis techniques as auger electron spectroscopy (AES),secondary ion mass spectrometry(SIMS), nuclear reaction analysis (NRA), electron microscopy and optical surface profiling have been applied for investigating erosion and deposition phenomena. the original plasma facing surface of the tiles were graphite (EK98) and plasma sprayed tungsten, respectively. the graphite tiles were used from 1991-1995 for about 1900 discharges and the tungsten tiles in 1996 for about 800 discharges...
Deuterium and impurity contamination of divertor tiles and collector probes of asdex-upgrade
(Fusion and plasma physics, 1998) Hildebrandt, D.; Akbi, Mohamed; Jüttner, B.; Rohde, V.; Schneider, W.
The uptake and release of hydrogen isotopes at the plasma-facing components in magnetic, confinement fusion devices affects the working gas recycling, the plasma behaviour and the tritium inventory [1]. This attracts considerable interest in the investigation of hydrogen trapping during plasma exposure. The most intensive plasma material interaction occurs on limiters and divertor plates. Post-mortem analysis of such components gives information on the total amount of hydrogen isotopes retained in the material after plasma exposure. Recent investigations of divertor tiles of ASDEX-UPGRADE have shown that the dominant trapped deuterium amount is contained in the deposited material at the surface [2]. This surface contamination consists mainly of carbon, boron and the hydrogenic isotopes. Movable collector probes have been applied to investigate the hydrogen trapping and impurity deposition under specific plasma conditions. In the present paper results on the impurity and deuterium contamination at the surface of collector samples are presented and compared with corresponding results from the divertor tiles. The collector samples were exposed to the scrape-off plasma of the main chamber (SOL-probe) and to the divertor plasma (DIV-probe)
Speed-up of high accuracy analog test stimulus optimization
(1999) Khouas, Abdelhakim; Derieux, Anne
Analog integrated circuit testing and diagnosis is a very challenging problem. The inaccuracy of measurements, the infinite domain of possible values and the parameter deviations are among the major difficulties. During the process of optimizing production tests, Monte Carlo simulation is often needed due to parameter variations, but because of its...
Fault Simulation for Analog Circuits Under Parameter Variations
(2000) Khouas, Abdelhakim; Derieux, Anne
Analog integrated circuit testing and diagnosis is a very challenging problem. The inaccuracy of measurements, the infinite domain of possible values and the parameter deviations are among the major difficulties. During the process of optimizing production tests, Monte Carlo simulation is often needed due to parameter variations, but because of its expensive computational cost, it becomes the bottleneck of such a process. This paper describes a new technique to reduce the number of simulations required during analog fault simulation. This leads to the optimization of production tests subjected to parameter variations. In Section 1 a review of the state of the art is presented, Section 2 introduces the algorithm and describes the methodology of our approach. The results on CMOS 2-stage opamp and Fifth-order Low-pass switched-capacitor Filter are given in Sections 3 and conclusions in Section 4
FDP: fault detection probability function for analog circuits
(IEEE, 2001) Khouas, Abdelhakim; Derieux, A.
In analog integrated circuits, process variations result in physical parameter variations. Simulated performance values must then be considered with their tolerance intervals. Consequently, contrarily to digital circuits where the outputs are either '0 or ' 1' such that we can decide without ambiguity whether a fault is detectable or not, for analog circuits fault detectability is still a vague problem since the fault can either be completely detectable, partially detectable or completely undetectable which makes it very difficult to take a decision. In order to solve this decision problem, we have introduced the fault detection probability (FDP) function which allows to formalize the problem of analog fault detection subjected to parameter variations
Pipelined sampled-delay focusing CMOS implementation for ultrasonic digital beamforming
(IEEE, 2003) Kassem, Abdallah; Wang, J.; Khouas, Abdelhakim; Boukadoum, Mounir
The real-time ultrasonic imaging system can be achieved using a digital beamforming (DBF) method. The critical part of the DBF is the real-time sampled-delay focusing (SDF) which requires a large number of memories (FIFO) to store the scanned information. The sampled-delay focusing technique is used to eliminate the use of the analog delay lines. This paper concerns the design and implementation of a pipelined sampled-delay architecture for ultrasonic digital beamforming. The design uses a minimum size look-up memory to store the initial scan information as opposed to previous approaches. The circuit is implemented in CMOS 0.18􀁐m technology and the resulting active layout area is 0.14 mm2, while its total power consumption is below 40 mW
Correction de trajectoires d’outils en usinage deux axes
(2003) Mir, Abdellah; Belaidi, Idir
Dans cet article, nous présentons un système de compensation de trajectoires d’outils permettant de corriger les trajectoires d’outils en fraisage 2 axes et de respecter ainsi une tolérance prescrite. Ce système est basé sur une stratégie de calcul de la déflexion d’outil s’appuyant sur un modèle d’effort de coupe statique et trois méthodes de correction différentes. L’étude expérimentale effectuée nous a permis d’étudier les performances de ces méthodes de correction en fonction des paramètres d’usinage : diamètre et longueur d’outil et avance par dent
Les méthodes d’approches en conception mécanique routinière
(2003) Semmoud, Fath-Eddine; Belaidi, Abderrahmane; Belaidi, Idir
Un objet (de type machine outil) passe nécessairement par la phase de conception qui est la première phase du cycle de vie d’un produit. Les très grandes avancées qu’a connu l’industrie et les développements de différents produits après la seconde guerre mondiale ont commencé après les deux guerres mondiales. La conception mécanique n’est pas un simple processus, elle est plutôt un ensemble de processus. Elle est l’incarnation de la connaissance des fonctions et des interactions des composants impliqués dans le mécanisme. Même si beaucoup de développements sont en cours actuellement, le processus reste à développer, analyser et, avec l’avènement de l’informatique, à formaliser mathématiquement et à implémenter. L’intégration de la conception mécanique, dans l’industrie algérienne comme pour les pays en voie de développement, sera importante dans l’optique d’assurer la maintenance de l'outil de production (dans un premier temps) et de développer des bases de connaissances qui seront la source de création de nouveaux produits pour un second. Nous proposons dans cet article la présentation de quelques méthodes d'approche utilisées et développées que nous avons pressenties nous permettre l’implémentation de conception routinière
Variable delay CMOS implementation for ultrasonic beamforming
(IEEE, 2003) Kassem, Abdallah; Wang, J.; Khouas, Abdelhakim; Boukadoum, Mounir
An ultrasound imaging systems require high resolution and real-time processing. The real-time imaging can be achieved using a digital beamforming (DBF) method. One of the main important parts of the DBF is the real-time delay calculation. The design and implementation of a pipelined architecture for the beamforming delay calculation is addressed. The design uses a minimum size look-up memory to store the initial scan information as opposed to previous approaches. The circuit is implemented in CMOS 0.18μm technology and the resulting layout area is 0.5 mm2, while a total power consumption of 20 mW
Application et adaptation de la triangulation de Delaunay pour la reconstruction de surfaces = Surface reconstruction using and adapting Delaunay triangulation
(2004) Challali, Mohand Oulhadj; Belaidi, Idir; Mohammedi, K.; Belaidi, Abderrahmane; Ishiomin, Guy
La reconstruction intéresse plusieurs domaines d'application et de recherche. Parmi ceux-ci nous trouvons: la génération d'un modèle CAO, la simulation, l'inspection et le contrôle, l'usinage, technologie des prothèses, assistance au diagnostic médical, vision robotique et artificielle, reconnaissance de terrains,…etc. Parmi les techniques de reconstruction d’une surface, nous trouvons celle qui procède par polyèdrisation du nuage de points [Ver 98], [Var 97]. Dans ce papier, nous proposons une telle technique basée sur l’adaptation et l’utilisation de la triangulation de Delaunay en dimension 2D1/2
Algorithmique pour la conversion par approximation de courbes de Bézier degré élevé : le modèle de rationnelle
(2004) Asma, Farid; Belaidi, Idir; Mohammedi, Kamal; Ischiomin, Guy; Challali, Mohand Oulhadj
Potential CADCAM applications of approximate conversion of degree élévated curves and surfaces may be numerous, but this requier the improved algorithms. To this effect, we introduce in this paper developpements of efficients algorithms to convert degree elevated Bézier rational curves, which caracterised by a minimal approximation error, reduced time of calculations and restricted number of spline curves. Besides, they offer a suitable flexibility by model transformations, without sophisticated calculations. The inverse algorithm for degree elevation of Bezier curves and the minimisation of the square norm in the Benstein polynomials basis are used for the degree reduction process, which is resolved by variable separation strategy in order to evoid the use of nonlinear methodes
Intégration du tolérancement dans les système de CFAO : méthode de synthèse statistique des tolérances par estimation des graduents
(2004) Boucherit, B.; Belaidi, Idir; Belaidi, Abderrahmane; Chalali, M.O.
L’intégration de la cotation automatique dans les systèmes de CFAO est plus que jamais d’actualité. Les systèmes actuellement disponibles restent incomplets et demeurent tous perfectibles ; les méthodes d’analyse et de synthèse font toujours l’objet de recherche et de développement continus. La synthèse statistique des tolérances par estimation des graduents jouit d’une simplicité de mise en oeuvre (utilisation des distributions discrètes au lieu des distributions continues), d’un temps de calcul réduit des dérivées par rapport à la méthodes des différences finis, d’une précision appréciable pour le calcul des tolérances intervenant dans le coût et la performance du produit (perte de qualité importante, coût de fabrication important)
A complete spurs distribution model for direct digital period synthesizers
(IEEE, 2005) Salomon, Max-Elie; Khouas, Abdelhakim; Savaria, Yvon
This paper presents a new, fully automated algorithm modeling the spurious frequencies in direct digital period synthesizers (DDPS). DDPS is a frequency synthesis technique that combines the speed and low jitter of a delay-locked-loop-based frequency multiplier, with the ability to digitally control the frequency. The algorithm is based on an analysis of the periodicity of the output signal produced by a DDPS circuit on which a time-domain Fourier analysis is performed. The resulting spectrum reflects two major known sources of spurious frequencies in DDPS: accumulator output truncation and delay line cell mismatch. Comparisons with results obtained from time-consuming simulations performed with SIMULINK and processed by FFT were performed to validate the model. An efficient implementation of the proposed algorithm allows comparing many different operating conditions that could not be analyzed with the SIMULINK model due to excessive processing time
Spurs modeling in direct digital period synthesizers related to phase accumulator truncation
(IEEE, 2005) Izouggaghen, Badre; Khouas, Abdelhakim; Savaria, Yvon
This paper presents an analytic model of the spurious noise frequencies in Direct Digital Period Synthesizer (DDPS) due to phase accumulator truncation. DDPS is a new technique for frequency synthesis that takes advantage of the speed and low jitter of a delay-lockedloop- based frequency multipliers and the ability to digitally control the frequency from the direct digital synthesis technique DDS [1-2]. The most important source of spurious noise frequencies in a DDPS circuit is the truncation of the output of its phase accumulator. Computing spectral analysis of DDPS circuit is a CPU time consuming task. Based on series of analytic calculations, a general and simple mathematical formula of the location of spurious frequencies and their magnitudes is predicted. This formula will help designers analyze and develop new DDPS circuits faster
Modeling Efficient Inductive Power Transfer Required To Supply Implantable Devices
(2005) Sehil, Mohamed; Sawan, Mohamad; Khouas, Abdelhakim
This paper presents a model for inductively coupled links with an integrated receiver on silicon. To be accurate, this model includes losses related to the integration of the receiver The modelling technique of the receiver coil has been verified using Agilent Momentum Electro-Magnetic simulations. This comprehensive model is employed to obtain maximum power efficiency by performing a discrete optimization of the geometric dimensions of the link coils. The optimized link can deliver 50mW to a visual cortical stimulator and monitoring devices with an efficiency of 21% at a distance of 1cm. The receiver has 4mm of diameter
Analysis of DC simulation convergence of nonlinear analog circuits with initial solution
(IEEE, 2005) Morneau, Michel; Khouas, Abdelhakim
Nouveau wrapper P1500 incorporant une structure bist pour le test des IP et des interconnexions d'un SoC
(IEEE, 2005) Larab, Abdelaziz; Khouas, Abdelhakim
Cette article présente une nouvelle architecture pour le test de modules pré-conçus « Intellectual Properties » (IP) et leurs interconnexions au niveau de systèmes intégrés sur une seule puce « System-On-Chip » (SOC). Cette nouvelle architecture de test combine la norme IEEE P1500 et la technique du test intégré « Built-In Self-Test » (BIST) dans une même structure de test configurable. L’architecture de test proposée permet principalement de réduire la surface de silicium additionnelle et d’assurer avec ses différents modes de test une bonne qualité de test sans dégradation de performances. Pour valider notre approche, nous avons comparé les surfaces obtenues pour certains circuits benchmark encapsulés en utilisant la nouvelle structure de test avec celles obtenues en utilisant une structure de test conventionnelle. Nous avons obtenu une moyenne de 5,35% de réduction de surface, le gain en surface varie entre 9,87% et 0,84%.
Generation de trajectoires d’outils : une approche simplifiée pour le calcul des intersections de surfaces subdivisées
(2005) Belaidi, Idir; Iloul, Amrane; Mohammedi, Kamal; Ishiomin, Guy
Dans ce papier, le problème de calcul d’intersection surface/surface intervenant lors de la génération de trajectoires d’outils en fraisage par contournage de surface gauches est considéré. A cet effet, nous proposons une approche simplifiée, basée sur une technique de subdivision récursive auto-adaptative, opérant sélectivement telle que la discrétisation effective d’un carreau de surface à usiner n’ait lieu qu’exclusivement au niveau des carreaux de surfaces où une intersection peut réellement exister. En outre, pour faciliter la procédure de vérification de l’existence d’intersections, le carreau de surface est assimilé à un plan dont la spécification géométrique de planéité est utilisée comme critère d’arrêt de la subdivision. Enfin, le calcul d’intersections «carreau de surface subdivisé / plan de coupe » est ramené à un problème simple de géométrie plane où les carreaux de surface sont assimilés à des quadrilatères représentés par leurs pôles respectifs
Measurement of delay mismatch due to process variations by means of modified ring oscillators
(IEEE, 2005) Zhou, B.; Khouas, Abdelhakim
A novel and effective test circuit to measure cell-tocell delay mismatch due to process variations is presented. A fully digital control circuit that efficiently realizes the technique is also described. The proposed test structure is realized by a series of modified ring oscillators that minimize factors of inaccuracy. The results of a simulation using 0.18μm CMOS technology show the feasibility of the technique. This test structure can be beneficial in thoroughly characterizing the effects of systematical process variations inside the chip.
Low Dead Time, Multi-hit FPGA-Based Time-to-Digital Converter
(IEEE, 2006) Amiri, Amir Mohammad; Boukadoum, Mounir; Khouas, Abdelhakim
This paper presents improvements on a novel FPGAbased multi-hit Time-to-Digital Converter (TDC) to measure time intervals with a resolution of 100ps and a variable dynamic range controlled by a binary coarse counter. We use a matrix topology to provide a two-level resolution, aiming to minimize the overall measurement time. The conventional dead time is eliminated by the continuous detection and processing of data by two delay matrices operating in parallel. A back-resetting scheme eliminates the erroneous multi-detection of an event along matrix tap lines. The circuit was tested on a XILINX SPARTAN-3 FPGA platform.