FPGA-based DTC method for three level inverter-fed induction motor speed

Abstract

The paper presents the natural extension DTC principle of three level diode clamped voltage inverter fed induction motor. This technique is based on a simple algorithm using look-up table for a three-level inverter established from a standard two-level inverter. The control algorithm is implemented using Field Programmable Gate Arrays (FPGA) with VHDL coding