FPGA-based DTC method for three level inverter-fed induction motor speed

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dc.contributor.authorDouib, Lyamine
dc.contributor.authorDouib, Lyamine
dc.contributor.authorBencheikh, Fares
dc.contributor.authorMetidji, B.
dc.contributor.authorKheldoun, Aissa
dc.date.accessioned2021-03-21T09:08:15Z
dc.date.available2021-03-21T09:08:15Z
dc.date.issued2017
dc.description.abstractThe paper presents the natural extension DTC principle of three level diode clamped voltage inverter fed induction motor. This technique is based on a simple algorithm using look-up table for a three-level inverter established from a standard two-level inverter. The control algorithm is implemented using Field Programmable Gate Arrays (FPGA) with VHDL codingen_US
dc.identifier.isbn978-1-5386-0687-2
dc.identifier.otherDOI: 10.1109/ICEE-B.2017.8192095
dc.identifier.urihttps://ieeexplore.ieee.org/document/8192095
dc.identifier.urihttps://dspace.univ-boumerdes.dz/handle/123456789/6644
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.relation.ispartofseries2017 5th International Conference on Electrical Engineering - Boumerdes (ICEE-B);
dc.subjectDTCen_US
dc.subjectVHDLen_US
dc.subjectFPGAen_US
dc.titleFPGA-based DTC method for three level inverter-fed induction motor speeden_US
dc.typeArticleen_US

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