Design implementation and Experimental Validation of a Digital PHase Locked Loop ( DPLL)

Abstract

The present work reports the simulation and realization of a Digital Phase-Locked Loop (DPLL).The circuit consists of three major blocks: a Phase Frequency Detector (PFD), an RC Low-PassFilter (LPF), and a Relaxation Voltage Controlled Oscillator (VCO). The analysis, design, andexamination of each blockwere carried out, resulting in a successful assembly of the entire DPLLcircuit. The designed PLL was simulated,measured, and then compared with the experimentalobservations using LM565 IC. The fi ndings demonstrate the PLL capability to achieve frequencysynchronization with minimal phase error at the desired frequency of 1 KHz, along with a widelock-in range.