On the Circuit-Level Reliability Degradation Due to AC NBTI Stress

Abstract

In this paper, an experimental analysis of the impactof dynamic negative bias temperature instability (NBTI) stresson the CMOS inverter dc response and temporal performanceis presented. We analyzed the circuit behavior subjected to acNBTI in the prospect to correlate the induced degradation withthat seen at PMOS device level. The results revealed that, whileac NBTI-induced shift of the inverter features shows both voltageand temperature dependence, it does not always exhibit stresstime dependence. Indeed, the time exponentnis found to dependon both voltage and temperature. The analysis of such behaviorwhen correlated with the PMOS threshold shift points towardthe coexistence of more than one physical mechanism behindthe degradation, where one mechanism could dominate the otherunder certain stress conditions. Depending on these conditions,circuit lifetime could be more or less affected