Publications Internationales
Permanent URI for this collectionhttps://dspace.univ-boumerdes.dz/handle/123456789/13
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Item Seminumerical technique for the analysis of integrated semiconductor devices(1994) Dehmas, Mokrane; Zitouni, Abdelkader; Bourdoucen, H.Item Quasi-static MoL-based approach for the analysis of multilayer transmission line structures(John Wiley & Sons, 1997) Zitouni, Abdelkader; Bourdoucen, H.; Nait Djoudi, T.Item Hydrogenated amorphous silicon nitride deposited by DC magnetron sputtering(Elsevier, 2006) Mokeddem, Kamel; Aoucher, M.; Smail, T.Item Investigation of single cell delay and delay mismatch in ring oscillator based test structure(2006) Zhou, Bo; Amiri, Amir Mohammad; Khouas, AbdelhakimIn previous work, we presented a test structure based on ring oscillator (RO) to measure single cell delay and delay mismatch, which can provide reliable information on intra-die and inter-die parameter variations. A delay cell of the configurable RO in the test structure considered for the computation technique consists of an inverter and a conducting transmission gate between adjacent cells. This paper will analyze the effects on delay cells of the transmission gates connecting to the output of inverters included in the active RO and investigate in depth delay mismatch in this RO based test structure. Monte Carlo simulation results reveal that the computation technique is applicable to derive delay mismatch between delay cells. A large number of post-layout simulations for different layout structures with different number of cells and different transistor sizes have been performed to analyze delay mismatch related to interconnect and device parameter variationsItem Spectral-domain integral-equation analysis of microstrip antenna working around 24 GHz(Wiley, 2000) Azrar, Arab; Aksas, Rabia; Vander Vorst, AndréItem Full-wave analysis of the broadband circular polarization microstrip patch antenna(Wiley, 2000) Azrar, Arab; Aksas, Rabia; Vander Vorst, AndreItem Full‐wave analysis of the broadband circular polarization microstrip patch antenna(Wiley, 2000) Azrar, Arab; Aksas, Rabia; Vander Vorst, AndreItem Novel analysis and design approaches of the planar antenna arrays(Springer, 2007) Azrar, Arab; Chemsa, Ali; Aksas, RabiaItem Voltage unbalance effects on induction motor performance(2006) Refoufi, Larbi; Bentarzi, Hamid; Dekhandji, Fatma ZohraThe reliability of electric drives and driven motors depends on the quality of the power supply voltage especially in the critical industrial process. In this work, a theoretical study of the effects of voltage unbalances, sags and swells on induction motor (IM) is performed by using the conventional method based on the theory of symmetrical components. For this study, MATLAB software program is developed for calculating currents, torque, power losses, temperature rises and derating factor. Besides, experiments have been carried out for obtaining currents, torque and power losses. An agreement that is found between the theoretical predictions and experimental data allows us to take into consideration the predicted derating factorItem TBSA : Threshold-Based Simulation Accuracy Method for Fast Analog DC Fault Simulation(Springer Science, 2006) Morneau, Michel; Khouas, AbdelhakimStarting from a good solution approximation has proved to be very efficient to reduce CPU time required by DC simulation of analog circuits. In order to obtain an additional speedup in DC fault simulation, this paper proposes a new criterion to end the Newton-Raphson (NR) iterative algorithm before convergence. In the case where an initial solution approximation is used, the analysis of the NR algorithm behavior until convergence is presented and a threshold-based simulation accuracy (TBSA) method is then proposed. TBSA stops the iterations when the solution at current NR iteration is enough accurate to immediately classify the fault. According to the detection thresholds, a CPU time/accuracy tradeoff is achieved without altering the fault classification results. The proposed method has been validated on 12 MOS and BJT benchmark circuits considering DC fault simulation under process parameter variations. TBSA is compared to two existing methods which are: standard simulation until convergence method which is accurate but requires a large CPU time, and single NR iteration method which is very fast but without any control over the accuracy. All the compared methods reuse the fault-free circuit results as initial solution for each faulty circuit simulation. It is shown that TBSA requires an intermediate number of NR iterations while achieving correct fault classification, especially for parametric faults which take advantage of using a more accurate initial solution.