Publications Scientifiques
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Item Single pulse charge pumping technique improvement for interface-states profiling in the channel of MOSFET devices(IEEE Transactions on Electron Devices, 2023) Messaoud, DhiaElhak; Djezzar, Boualem; Boubaaya, Mohamed; Benabdelmoumene, Abdelmadjid; Zatout, Boumediene; Chenouf, Amel; Zitouni, AbdelkaderThis paper presents the separated single pulse charge pumping (SSPCP) technique, an improvement over conventional single pulse charge pumping (CSPCP) for analyzing metal oxide semiconductor field-effect transistor (MOSFET) degradation. SSPCP separates the measurement of source and drain currents (Is and Id ), enabling the localization of interface traps (Nit) near these regions. Experimental validation shows that SSPCP achieves comparable results to CSPCP with a maximum measurement error of 5%. The technique is particularly useful for studying stress-induced localized degradation profiling, allowing for the exploration of non-uniform stress (e.g., hot-carrier injection) and uniform stress (e.g., negative bias temperature instability) in transistors with short channels. SSPCP effectively analyzes localized degradation and identifies differences in stress-induced degradation between the source and drain regions, making it a valuable tool in semiconductor device characterization.Item Single Pulse Charge Pumping Technique Improvement for Interface-States Profiling in the Channel of MOSFET Devices(2023) Messaoud, Dhia Elhak; Djezzar, Boualem; Boubaaya, Mohamed; Benabdelmoumene, Abdelmadjid; Zatout, Boumediene; Chenouf, Amel; Zitouni, AbdelkaderThis paper presents the separated single pulse charge pumping (SSPCP) technique, an improvement over conventional single pulse charge pumping (CSPCP) for analyzing metal oxide semiconductor field-effect transistor (MOSFET) degradation. SSPCP separates the measurement of source and drain currents $({I}_{ {s}}$ and ${I}_{ {d}}$ ), enabling the localization of interface traps $({N}_{ {it}})$ near these regions. Experimental validation shows that SSPCP achieves comparable results to CSPCP with a maximum measurement error of 5%. The technique is particularly useful for studying stress-induced localized degradation profiling, allowing for the exploration of non-uniform stress (e.g., hot-carrier injection) and uniform stress (e.g., negative bias temperature instability) in transistors with short channels. SSPCP effectively analyzes localized degradation and identifies differences in stress-induced degradation between the source and drain regions, making it a valuable tool in semiconductor device characterization.Item Fast methods for studying the effect of electrical stress on SiO2 dielectrics in Metal-Oxide-Semiconductor Field-Effect transistors(Pleiades Publishing, 2023) Messaoud, Dhia Elhak; Djezzar, Boualem; Boubaaya, Mohamed; Chenouf, Amel; Benabdelmoumene, Abdelmadjid; Zatout, Boumediene; Zitouni, AbdelkaderThis work implements three fast measurement techniques based on the measure–stress–measure (MSM) method. These techniques, namely, measuring–around–, one–point on–the–fly (OTF), and pulsed current-voltage (PIV), were used to characterize three different technologies of metal–oxide–semiconductor field-effect transistors (MOSFETs) with same gate dielectric silicon–dioxide (SiO2) and various thicknesses = 20 nm, 4 nm, 2.3 nm. Moreover, well–configured electrical stress biasing has been performed to discuss the dielectric degradation of these devices using those characterization techniques. The pros and cons of the used techniques are well discussed based on our results. Furthermore, experimental results showed that threshold voltage shift () follows a power law time dependence with time exponent (n) being 0.16 for molecular hydrogen (H2) diffusing species and 0.25 for hydrogen atoms (H) diffusing species. We have found that the thicker the SiO2 dielectric the more the oxide traps () contribute to the resulting degradation. However, the dependency between SiO2 dielectric thickness and oxide traps could not be necessarily linear.Item Metal-oxide-semiconductor field-effect transistor (MOSFET) pulsed current-voltage characterization technique: design and discussion(Pleiades Publishing, 2023) Messaoud, Dhia Elhak; Djezzar, Boualem; Boubaaya, Mohamed; Benabdelmoumene, Abdelmadjid; Zatout, Boumediene; Chenouf, Amel; Zitouni, AbdelkaderIn this paper, we implement the pulsed current–voltage (PIV) technique for the metal-oxide-semiconductor field-effect transistor (MOSFET) device’s ultrafast characterization based on the OpAmp amplifier OPA818. The latter dropped down the measurement time for a whole MOSFET characteristic to = 50 ns as an enhancement. Furthermore, a study concerning the technique’s dependency on measurement time (), channel length (), and channel width () is accomplished. It is found that the distortion in the technique’s results, labeled as hysteresis, is inversely proportional to measurement time and it increases dramatically with very low values of . Also, the results show that PIV could have a somehow direct proportionality to channel length, and it is justified by the gate/drain capacitance () effect. On the other hand, the technique shows no dependency on channel width at all. Moreover, as measurements limitations, the results couldn’t record drain currents less than ≈ 10–7 A, this makes PIV limited to the study of threshold voltage degradation () only. However, this issue is well discussed and solutions have been proposed.Item On the Circuit-Level Reliability Degradation Due to AC NBTI Stress(IEEE Transactions on Device and Materials Reliability, 2016) Chenouf, Amel; Djezzar, Boualem; Benabdelmoumene, Abdelmadjid; Tahi, HakimIn this paper, an experimental analysis of the impactof dynamic negative bias temperature instability (NBTI) stresson the CMOS inverter dc response and temporal performanceis presented. We analyzed the circuit behavior subjected to acNBTI in the prospect to correlate the induced degradation withthat seen at PMOS device level. The results revealed that, whileac NBTI-induced shift of the inverter features shows both voltageand temperature dependence, it does not always exhibit stresstime dependence. Indeed, the time exponentnis found to dependon both voltage and temperature. The analysis of such behaviorwhen correlated with the PMOS threshold shift points towardthe coexistence of more than one physical mechanism behindthe degradation, where one mechanism could dominate the otherunder certain stress conditions. Depending on these conditions,circuit lifetime could be more or less affectedItem Investigation of NBTI degradation on power VDMOS transistors under magnetic field(IEEE, 2014) Tahi, Hakim; Benmessai, Karim; Le Floch, Jean Michel; Boubaaya, Mohamed; Tahanout, Cherifa; Djezzar, Boualem; BENABDELMOMENE, Abdelmadjid; Goudjil, Mohamed; Chenouf, AmelIn this paper, we report an experimental evidence of the impact of applied a low magnetic field (B<;100 Gauss) during negative bias temperature instability (NBTI) stress and recovery, on commercial power double diffused MOS transistor (VDMOS). We show that both interface (ΔN it ) and oxide trap (ΔN ot ) induced by NBTI stress decrease by applied magnetic field. This decrease is more pronounced as the magnetic field is high. In addition, the recovery of NBTI induced threshold voltage shift (ΔV th ) is relatively important with applied magnetic field.Item Charge Pumping,GeometricComponent and Degradation ParametersExtraction in MOSFETDevices(IEEE, 2015) Tahi, Hakim; Tahanout, Cherifa; Djezzar, Boualem Djezzar; Boubaaya, Mohamed; Abdelmadjid, Benabdelmoumene; Chenouf, AmelIn this paper, we model the geometric component of charge pumping technique (CP). Base on this proposed model, wehave established ananalyticequation for charge pumping current. This equation seems to be an universal one since it is in agreement with CP experimental data of different technologies devices.Instead the classical considerations regarding a parasitic nature of the geometric component, we have demonstrated, in this work, that it can be used to estimate the negative bias temperature (NBTI)induced mobility degradationusing the charge pumping basedmethods such as on-the-fly interface trap (OTFIT).Item Sizing of the CMOS 6T-SRAM cell for NBTI ageing mitigation(IEEE, 2020) Chenouf, Amel; Djezzar, Boualem; Bentarzi, Hamid; Benabdelmoumene, AbdelmadjidThis study presents a negative bias temperature instability (NBTI) mitigation design technique for CMOS 6T-static random access memory (6T-SRAM) cells. The proposed approach is based on transistor sizing technique. It consists of sizing the nMOS access transistors of the cell to alleviate NBTI ageing occurring in its pMOS pull-up transistors threatening the cell stability. Once the access transistors are sized for a better hold static noise margin under NBTI, the other transistors of the 6T-SRAM cell could be properly sized for improved read stability and write-abilityItem Oxide trap annealing by H2 cracking at e'center under NBTI stress(IEEE, 2012) Tahanout, Cherifa; Nadji, Becharia; Tahi, Hakim; Djezzar, Boualem; Benabdelmoumene, Abdelmadjid; Chenouf, Amel