Publications Internationales
Permanent URI for this collectionhttps://dspace.univ-boumerdes.dz/handle/123456789/13
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Item Methodology for Fast and Accurate Analog Production Test(1999) Khouas, Abdelhakim; Derieux, AnneThis paper describes a new technique to reduce the number of simulations required during analog fault simulation. The method takes into account process parameter variations and aims to reduce the number of the computational expensive Monte Carlo simulations often required during analog fault simulation. In section I a review of the state of the art.Item Speed-up of High Accurate Analog Test Stimulus(1999) Khouas, Abdelhakim; Derieux, AnneAnalog integrated circuit testing and diagnosis is a very challenging problem. The inaccuracy of measurements, the innite domain of possible values and the parameter deviations are among the major diOEculties. During the process of optimizing production tests, Monte Carlo simulation is often needed due to parameter variations, but because of its expensive computational cost, it becomes the bottleneck of such a process. This paper describes a new technique to reduce the number of simulations required during analog fault simulation. This leads to the optimization of production tests subjected to parameter variations. In section I a review of the state of the art is presented, section II introduces the algorithm and describes the methodology of our approach. The results on CMOS 2-stage opamp and conclusions are given in sections III and IVItem Analog Fault Detection based on Statistical Analysis(Hal, 2000) Khouas, Abdelhakim; Derieux, AnneIn analog circuits, process variations result in physical parameter variations. Simulated values must then be considered with there tolerance intervals. Consequently, contrarily to digital circuits where the outputs are either '0' or '1' such that we can decide without ambiguity whether a fault is detectable or not, for analog circuits the fault detectability is a vague problem as the fault can either be completely detectable, partially detectable or completely undetectable which makes it very diOEcult to take a decision. In order to solve this decision problem, we have introduced the probability to detect fault (PDF) function which allows to formalize the problem of analog fault detection under parameter variationsItem Optimized Statistical Analog Fault Simulation(2001) Khouas, Abdelhakim; Dessouky, Mohamed; Derieux, AnneA new statistical method for analog fault simulation is presented. The method takes into account process parameter variations and aims to reduce the number of the computational expensive Monte Carlo simulations often required during analog fault simulation. The technique is illustrated by means of a fifth-order low-pass switched-capacitor filterItem Investigation of single cell delay and delay mismatch in ring oscillator based test structure(2006) Zhou, Bo; Amiri, Amir Mohammad; Khouas, AbdelhakimIn previous work, we presented a test structure based on ring oscillator (RO) to measure single cell delay and delay mismatch, which can provide reliable information on intra-die and inter-die parameter variations. A delay cell of the configurable RO in the test structure considered for the computation technique consists of an inverter and a conducting transmission gate between adjacent cells. This paper will analyze the effects on delay cells of the transmission gates connecting to the output of inverters included in the active RO and investigate in depth delay mismatch in this RO based test structure. Monte Carlo simulation results reveal that the computation technique is applicable to derive delay mismatch between delay cells. A large number of post-layout simulations for different layout structures with different number of cells and different transistor sizes have been performed to analyze delay mismatch related to interconnect and device parameter variationsItem TBSA : Threshold-Based Simulation Accuracy Method for Fast Analog DC Fault Simulation(Springer Science, 2006) Morneau, Michel; Khouas, AbdelhakimStarting from a good solution approximation has proved to be very efficient to reduce CPU time required by DC simulation of analog circuits. In order to obtain an additional speedup in DC fault simulation, this paper proposes a new criterion to end the Newton-Raphson (NR) iterative algorithm before convergence. In the case where an initial solution approximation is used, the analysis of the NR algorithm behavior until convergence is presented and a threshold-based simulation accuracy (TBSA) method is then proposed. TBSA stops the iterations when the solution at current NR iteration is enough accurate to immediately classify the fault. According to the detection thresholds, a CPU time/accuracy tradeoff is achieved without altering the fault classification results. The proposed method has been validated on 12 MOS and BJT benchmark circuits considering DC fault simulation under process parameter variations. TBSA is compared to two existing methods which are: standard simulation until convergence method which is accurate but requires a large CPU time, and single NR iteration method which is very fast but without any control over the accuracy. All the compared methods reuse the fault-free circuit results as initial solution for each faulty circuit simulation. It is shown that TBSA requires an intermediate number of NR iterations while achieving correct fault classification, especially for parametric faults which take advantage of using a more accurate initial solution.Item Multicoils-based inductive links dedicated to power up implantable medical devices: Modeling, design and experimental results(Springer Science, 2009) Sawan, Mohamad; Hashemi, Saeid; Sehil, Mohamed; Khouas, AbdelhakimWe present in this paper a new topology of inductively-coupled links based on a monolithic multi-coils receiver. A model is built to characterize the proposed structure using Matlab and is verified employing simulation tools under ADS electromagnetic environment. This topology accounts for the losses associated with the receiver micro-coil including substrate and oxide layers. The geometry of micro-coils significantly desensitizes the link to both angular and side misalignments. A custom fabrication process using 1 micron metal thickness is also presented by which two sets of micro-coils varying in the number of coils are realized. The first set possesses one coil 4 mm of diameter and represents a power efficiency close to 4% while the second set possesses multi-coils with an efficiency of 18%. The resulting optimized link can deliver up to 50 mW of power to power up an implantable device either sensor or stimulator. The experimental results for the prototypes are remarkably in agreement with those obtained from simulated models and circuitsItem Spur Model for a Fixed-Frequency Signal Subject to Periodic Jitter(IEEE, 2008) Salomon, Max-Elie; Izouggaghen, Badre; Khouas, Abdelhakim; Savaria, YvonThis paper presents an automated algorithm that is capable of predicting both the location and magnitude of spurs that are caused by different sources of jitter on a periodic signal. A practical circuit that produces this kind of jittered periodic signal is the direct digital period synthesis (DDPS) circuit that can be used as a flexible clock source for various applications such as adjusting a sampling rate in a measurement and signal processing. Points of interest with clocks that are subject to periodic perturbations are their spectral purity and jitter characteristics. Our algorithm is applied to the DDPS to greatly reduce the simulation time that is needed to accurately compute the spectrum of the signal and its spurious frequency content. The method is used to explore how the operating parameters of the DDPS influence the spectral purity of its output. The generic analysis method that has been used in this paper can be transposed to fractional- N synthesizers, delay-line-based direct digital synthesizers, or serializersItem A Multihit Time-to-Digital Converter Architecture on FPGA(IEEE, 2009) Amiri, Amir Mohammad; Boukadoum, Mounir; Khouas, AbdelhakimWe present a multihit time-to-digital converter (TDC) architecture implemented in a field-programmable gate array (FPGA) with minimized timing overhead. The TDC circuit provides two-level fine-time interpolation. The fine interpolator is a matrix of Vernier delay cells interconnected in a topology to provide two propagation paths for the incoming data pulse. Two methods of calibration are presented to estimate the component delays. The TDC circuit achieves time measurements with a resolution of 75 ps with an average precision of ~ 300 ps and is capable of detecting incoming pulses at a distance of 7.5 ns or more from each otherItem Pseudorandom stimuli generation for testing time-to-digital converters on an FPGA(IEEE, 2009) Amiri, Amir Mohammad; Khouas, Abdelhakim; Boukadoum, MounirThis paper presents a pulse generator circuit that produces a stream of pulses at pseudorandom time intervals. The proposed circuit may serve as a stimulus generator for code density testing of time-to-digital converters (TDCs). The functional behavior of the circuit was first investigated with a software model coded in C ++. The software simulation showed that the interpulse intervals only uniformly cover their domain at a given resolution if the greatest common divisor between the intervals and the observation window is 1 with respect to a common reference clock. In a second step, the circuit was implemented in hardware using very high-speed integrated circuit (VHSIC) hardware description language (VHDL) and tested on a Xilinx Spartan-3 field-programmable gate array (FPGA) platform. The pulse density histograms obtained from the software and hardware test cases show pulse distributions with nonlinearity values within one least significant bit (LSB). In the end, the circuit was used as a stimulus generator for code density testing of a TDC circuit on an FPGA